S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of.

Slides:



Advertisements
Similar presentations
Design and Implementation of VLSI Systems (EN1600)
Advertisements

Transmission Gate Based Circuits
CSET 4650 Field Programmable Logic Devices
Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout
Introduction to CMOS VLSI Design Lecture 19: Design for Skew David Harris Harvey Mudd College Spring 2004.
Chapter 09 Advanced Techniques in CMOS Logic Circuits
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN01600) Lecture 19: Combinational Circuit Design (1/3) Prof. Sherief Reda Division of Engineering,
Introduction to CMOS VLSI Design Clock Skew-tolerant circuits.
Combinational circuits Lection 6
Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE VLSI Circuit Design Lecture 9 - Combinational.
Designing Combinational Logic Circuits: Part2 Alternative Logic Forms:
S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN1600S08) Lecture12: Logical Effort (1/2) Prof. Sherief Reda Division of Engineering,
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 14: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 20: Circuit Design Pitfalls Prof. Sherief Reda Division of Engineering,
1 Clockless Logic Montek Singh Tue, Mar 16, 2004.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 11: Logical Effort (1/2) Prof. Sherief Reda Division of Engineering, Brown.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 15: Interconnects & Wire Engineering Prof. Sherief Reda Division of Engineering,
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007.
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 22: Sequential Circuit Design (1/2) Prof. Sherief Reda Division of Engineering,
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 20: Combinational Circuit Design (2/3) Prof. Sherief Reda Division of Engineering,
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 31: Array Subsystems (SRAM) Prof. Sherief Reda Division of Engineering,
Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 22: Material Review Prof. Sherief Reda Division of Engineering, Brown University.
Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.
Introduction to CMOS VLSI Design Circuit Families.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture10: Delay Estimation Prof. Sherief Reda Division of Engineering, Brown University.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 21: Differential Circuits and Sense Amplifiers Prof. Sherief Reda Division.
Circuit Families Adopted from David Harris of Harvey Mudd College.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.
S. Reda VLSI Design Design and Implementation of VLSI Systems (EN1600) lecture09 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008.
Lecture 5 – Power Prof. Luke Theogarajan
S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 13: Logical Effort (2/2) Prof. Sherief Reda Division of Engineering, Brown.
Design and Implementation of VLSI Systems (EN0160)
EE141 © Digital Integrated Circuits 2nd Combinational Circuits 1 Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 5, 2014 Dynamic Logic Midterm.
Lecture 7: Power.
Digital CMOS Logic Circuits
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 23: Sequential Circuit Design (1/3) Prof. Sherief Reda Division of Engineering,
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 17: Static Combinational Circuit Design (1/2) Prof. Sherief Reda Division.
Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 18: Static Combinational Circuit Design (2/2) Prof. Sherief Reda Division.
VLSI Digital Systems Design Alternatives to Fully-Complementary CMOS Logic.
Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 10.1 EE4800 CMOS Digital IC Design & Analysis Lecture 10 Combinational Circuit Design Zhuo Feng.
1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
MOS Transistors The gate material of Metal Oxide Semiconductor Field Effect Transistors was original made of metal hence the name. Present day devices’
Microelectronic Circuits, Sixth Edition Sedra/Smith Copyright © 2010 by Oxford University Press, Inc. C H A P T E R 14 Advanced MOS and Bipolar Logic Circuits.
EE415 VLSI Design DYNAMIC LOGIC [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE 447 VLSI Design Lecture 8: Circuit Families.
CMOS DYNAMIC LOGIC DESIGN
Ratioed Circuits Ratioed circuits use weak pull-up and stronger pull-down networks. The input capacitance is reduced and hence logical effort. Correct.
Notices You have 18 more days to complete your final project!
Chapter 1 Combinational CMOS Logic Circuits Lecture # 4 Pass Transistors and Transmission Gates.
ECE442: Digital ElectronicsSpring 2008, CSUN, Zahid Static CMOS Logic ECE442: Digital Electronics.
Lecture 10: Circuit Families. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 10: Circuit Families2 Outline  Pseudo-nMOS Logic  Dynamic Logic  Pass Transistor.
Advanced VLSI Design Unit 04: Combinational and Sequential Circuits.
Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: November 1, 2010 Dynamic Logic.
Introduction to CMOS VLSI Design Lecture 9: Circuit Families
Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Properties of Complementary CMOS Gates.
Solid-State Devices & Circuits
Dynamic Logic.
EE141 Combinational Circuits 1 Chapter 6 (I) Designing Combinational Logic Circuits Dynamic CMOS LogicDynamic CMOS Logic V1.0 5/4/2003.
Static Logic vs. Pseudo-nMOS Static Logic includes pull-up and pull-down networks - 2n transistors for n-input function. Pseudo-nMOS - n+1 transistors.
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University
1 Recap: Lecture 4 Logic Implementation Styles:  Static CMOS logic  Dynamic logic, or “domino” logic  Transmission gates, or “pass-transistor” logic.
Lecture 10: Circuit Families
Lecture 10: Circuit Families
Day 21: October 29, 2010 Registers Dynamic Logic
Combinational Circuit Design
Lecture 10: Circuit Families
Presentation transcript:

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07 Dynamic logic Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate Dynamic circuit operation is divided into two modes: precharge and evaluate

S. Reda EN160 SP’07 What if the input is ON during precharge? What if pulldown network is ON during precharge? –Contention arises because both pMOS and nMOS will be ON Use series evaluation transistor to prevent fight.

S. Reda EN160 SP’07 Logic effort for dynamic circuits Very fast with very low logical effort

S. Reda EN160 SP’07 Dynamic circuits have a problem: Monotonicity requirement Dynamic gates require monotonically rising inputs during evaluation –0 → 0 –0 → 1 –1 → 1 –But not 1 → 0

S. Reda EN160 SP’07 Implications of Monotonicity But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another!

S. Reda EN160 SP’07 Domino Logic Follow dynamic stage with inverting static gate –Dynamic / static pair is called domino gate –Produces monotonic outputs

S. Reda EN160 SP’07 Domino optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic 8-input multiplexer built from two 4-input dynamic multiplexers

S. Reda EN160 SP’07 Dual-Rail Domino Domino only performs noninverting functions: –AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem –Takes true and complementary inputs –Produces true and complementary outputs sig_hsig_lMeaning 00Precharged 01‘0’ 10‘1’ 11invalid

S. Reda EN160 SP’07 Leakage problems Dynamic node floats high during evaluation –Transistors are leaky (I OFF  0) –Dynamic value will leak away over time –Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node –Must be weak enough not to fight evaluation

S. Reda EN160 SP’07 Charge sharing Dynamic gates suffer from charge sharing Solution: add secondary precharge transistors Typically need to precharge every other node Big load capacitance C Y helps as well

S. Reda EN160 SP’07 Domino Summary Domino logic is attractive for high-speed circuits –1.5 – 2x faster than static CMOS –But many challenges: Monotonicity, leakage, charge sharing, noise, and high dynamic power Widely used in high-performance microprocessors Static CMOS Ratioed Circuits Cascode Voltage Switch Logic Pass-transistor Circuits Dynamic Circuits Circuit Families