Hardware Implementation of Antenna Beamforming using Genetic Algorithm Kevin Hsiue Bryan Teague.

Slides:



Advertisements
Similar presentations
Give qualifications of instructors: DAP
Advertisements

Vector Processing. Vector Processors Combine vector operands (inputs) element by element to produce an output vector. Typical array-oriented operations.
VLSI Communication SystemsRecap VLSI Communication Systems RECAP.
ProActive Task Manager Component for SEGL Parameter Sweeping Natalia Currle-Linde and Wasseim Alzouabi High Performance Computing Center Stuttgart (HLRS),
CS 151 Digital Systems Design Lecture 37 Register Transfer Level
1/44 1. ZAHRA NAGHSH JULY 2009 BEAM-FORMING 2/44 2.
Order-Independent Texture Synthesis Li-Yi Wei Marc Levoy Gcafe 1/30/2003.
Behavioral Design Outline –Design Specification –Behavioral Design –Behavioral Specification –Hardware Description Languages –Behavioral Simulation –Behavioral.
Hardware-based Load Generation for Testing Servers Lorenzo Orecchia Madhur Tulsiani CS 252 Spring 2006 Final Project Presentation May 1, 2006.
Pipelined Computations Divide a problem into a series of tasks A processor completes a task sequentially and pipes the results to the next processor Pipelining.
1 An Exploration of the MPEG Algorithm Using Latency Insensitive Design EE249 Presentation (12/04/1999) Trevor Meyerowitz Mentored by: Luca Carloni.
Evolutionary Computation Application Peter Andras peter.andras/lectures.
Compiler Optimization-Space Exploration Adrian Pop IDA/PELAB Authors Spyridon Triantafyllis, Manish Vachharajani, Neil Vachharajani, David.
Sept EE24C Digital Electronics Project Design of a Digital Alarm Clock.
Development in hardware – Why? Option: array of custom processing nodes Step 1: analyze the application and extract the component tasks Step 2: design.
C. Benatti, 3/15/2012, Slide 1 GA/ICA Workshop Carla Benatti 3/15/2012.
SOFT COMPUTING (Optimization Techniques using GA) Dr. N.Uma Maheswari Professor/CSE PSNA CET.
DLS Digital Controller Tony Dobbing Head of Power Supplies Group.
High Performance, Pipelined, FPGA-Based Genetic Algorithm Machine A Review Grayden Smith Ganga Floora 1.
Section 10: Advanced Topics 1 M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi.
CMOS Design Methods.
Hardware Implementation of a Memetic Algorithm for VLSI Circuit Layout Stephen Coe MSc Engineering Candidate Advisors: Dr. Shawki Areibi Dr. Medhat Moussa.
Optimization Problems - Optimization: In the real world, there are many problems (e.g. Traveling Salesman Problem, Playing Chess ) that have numerous possible.
RoBach A Case Study in the Use of Genetic Algorithms for Automatic Music Composition.
Quadratic Programming Solver for Image Deblurring Engine Rahul Rithe, Michael Price Massachusetts Institute of Technology.
1 Towards Optimal Custom Instruction Processors Wayne Luk Kubilay Atasu, Rob Dimond and Oskar Mencer Department of Computing Imperial College London HOT.
NSF SURE Program, Summer 2002 / Clemson University, Clemson, SC 1 Broadband Arrays and Switching Antennas Dan Palecek, SD School of Mines and Technology,
S J van Vuuren The application of Genetic Algorithms (GAs) Planning Design and Management of Water Supply Systems.
Ultrasonic Beam-forming with the Genetic Algorithm Andrew Fiss, Vassar College Nathan Baxter, Ohio Northern University Jerry Magnan, Florida State University.
On Tuning Microarchitecture for Programs Daniel Crowell, Wenbin Fang, and Evan Samanas.
Radix-2 2 Based Low Power Reconfigurable FFT Processor Presented by Cheng-Chien Wu, Master Student of CSIE,CCU 1 Author: Gin-Der Wu and Yi-Ming Liu Department.
Lecture 16: Reconfigurable Computing Applications November 3, 2004 ECE 697F Reconfigurable Computing Lecture 16 Reconfigurable Computing Applications.
1 A New Method for Composite System Annualized Reliability Indices Based on Genetic Algorithms Nader Samaan, Student,IEEE Dr. C. Singh, Fellow, IEEE Department.
Midterm Presentation Performed by: Ron Amit Supervisor: Tanya Chernyakova Semester: Spring Sub-Nyquist Sampling in Ultrasound Imaging.
Field Programmable Port Extender (FPX) 1 Modular Design Techniques for the FPX.
Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.
Genetic Algorithms What is a GA Terms and definitions Basic algorithm.
ECE 103 Engineering Programming Chapter 52 Generic Algorithm Herbert G. Mayer, PSU CS Status 6/4/2014 Initial content copied verbatim from ECE 103 material.
A l a p a g o s : a generic distributed parallel genetic algorithm development platform Nicolas Kruchten 4 th year Engineering Science (Infrastructure.
CORDIC-Based Processor
Sensor testing and validation plans for Phase-1 and Ultimate IPHC_HFT 06/15/ LG1.
Survey of multicore architectures Marko Bertogna Scuola Superiore S.Anna, ReTiS Lab, Pisa, Italy.
GENETIC ALGORITHM Basic Algorithm begin set time t = 0;
Authors: Soamsiri Chantaraskul, Klaus Moessner Source: IET Commun., Vol.4, No.5, 2010, pp Presenter: Ya-Ping Hu Date: 2011/12/23 Implementation.
GAIA (Genetic Algorithm Interface Architecture) Requirements Analysis Document (RAD) Version 1.0 Created By: Charles Hall Héctor Aybar William Grim Simone.
Genetic algorithms: A Stochastic Approach for Improving the Current Cadastre Accuracies Anna Shnaidman Uri Shoshani Yerach Doytsher Mapping and Geo-Information.
Genetic Search Algorithms Matt Herbster. Why Another Search?  Designed in the 1950s, heavily implemented under John Holland (1970s)  Genetic search.
(Genetic Algorithm Interface Architecture) Final Presentation CS 425 Created By: Chuck Hall Simone Connors Héctor Aybar Mike Grim.
Genetic Algorithms. Underlying Concept  Charles Darwin outlined the principle of natural selection.  Natural Selection is the process by which evolution.
VLSI Design of 2-D Discrete Wavelet Transform for Area-Efficient and High- Speed Image Computing - End Presentation Presentor: Eyal Vakrat Instructor:
Processor Organization and Architecture Module III.
An FFT for Wireless Protocols Dr. J. Greg Nash Centar ( HAWAI'I INTERNATIONAL CONFERENCE ON SYSTEM SCIENCES Mobile.
1 An FPGA Implementation of the Two-Dimensional Finite-Difference Time-Domain (FDTD) Algorithm Wang Chen Panos Kosmas Miriam Leeser Carey Rappaport Northeastern.
Antenna Arrays and Automotive Applications
Multi-cellular paradigm The molecular level can support self- replication (and self- repair). But we also need cells that can be designed to fit the specific.
AN OPTIMIZATION DESIGN OF ARTIFICIAL HIP STEM BY GENETIC ALGORITHM AND PATTERN CLASSIFICATION.
EVOLUTIONARY SYSTEMS AND GENETIC ALGORITHMS NAME: AKSHITKUMAR PATEL STUDENT ID: GRAD POSITION PAPER.
Resource Sharing in LegUp. Resource Sharing in High Level Synthesis Resource Sharing is a well-known technique in HLS to reduce circuit area by sharing.
Genetic Algorithm(GA)
Genetic (Evolutionary) Algorithms CEE 6410 David Rosenberg “Natural Selection or the Survival of the Fittest.” -- Charles Darwin.
Benjamin Baggett M.S. Thesis Project, Virginia Tech Advisor: Dr. Timothy Pratt Keywords: Genetic algorithm, particle swarm optimization, aperiodic array,
Backprojection Project Update January 2002
A Review of Processor Design Flow
Modified Crossover Operator Approach for Evolutionary Optimization
Spectrum Sensing with Software Radios
Team Skill 6 - Building The Right System Part 1: Applying Use Cases
6.375 Final Project March 2,
IMPLEMENTATION OF SMART ANTENNA USING
Embedded Sound Processing : Implementing the Echo Effect
Coevolutionary Automated Software Correction
Presentation transcript:

Hardware Implementation of Antenna Beamforming using Genetic Algorithm Kevin Hsiue Bryan Teague

Genetic Algorithm Optimization Initial Population Selection for favorable traits Reproduction of most favorable Mutation adds variation Selection prefers favorable mutation Reproduction and repeat…

Antenna Beamforming  What is antenna beamforming?  Process of controlling relative phase of individual antennas to create a desired radiation pattern  Main beam position, sidelobe levels, and null position can be controlled Ruckus ZoneFlex 7962 Wireless Router ANTENNAS

Project Objectives Goal: Implement genetic algorithm processor in hardware and demonstrate using antenna beamforming problem  Genetic algorithms and beamforming equations are each inherently parallelizable  Complex beamforming problems currently solved using genetic algorithms (GAs) in software  GAs have previously had mixed success in hardware

Project Objectives  Can hardware improve convergence rate of optimization?  Can flexibility be retained in hardware?  Can a hardware GA be scaled up to complicated beamforming problems?  Can hardware be used to solve GAs in “real-time”?

Implementation Block Diagram Basic Genetic Algorithm Block Diagram

Implementation Block Diagram Detailed Genetic Algorithm Block Diagram

System Data Flow User Interface and Data Flow

Microarchitectural Description Population Sequential Genetic Algorithm

Video – Bluespec Simulation Legend Solution Ideal  Ideal curve generated from Python reference design  Solution generate with Bluespec simulation

Implementation Evaluation * Assumes 20 MHz clock frequency ** Does not include SceMi interface

Microarchitectural Description 2 Pipelined Genetic Algorithm

Microarchitectural Description 2 Cordic functions pipelined to accept one sample per clock cycle

Implementation Evaluation 2 * Assumes 20 MHz clock frequency ** Does not include SceMi interface *** Assumes 50 MHz clock frequncy

Design Exploration  Scale to models of larger arrays  PAR successful for 32 element antenna array on V5 (50 MHz)  Synthesis suggests 128 element on V7 (100 MHz)  What are the limits?  When does a new architecture make sense?

Design Exploration  Add mutation controller  Tracks rate of change in cost function  Controls mutation parameters accordingly  More complicated antenna cost function  Multiple Cordic processors operating on single chromosome  New problem, same architecture?

Summary  Can hardware improve convergence rate of optimization?  3 orders of magnitude compared to Python implementation  Can flexibility be retained in hardware?  Multiple sorting algorithms explored  Discrete modules with identical interfaces  Important tuning parameters are be stored in registers  Can a hardware GA be scaled up to complicated beamforming problems?  Yes! (32 element on V5, 128 element on V7)  Can hardware be used to solve GAs in “real-time”?  Yes, for small problems, but limitations have not been explored  150 generations for 8-element array = ~41 kHz  How does the convergence scale?