A Look at Chapter 4: Circuit Characterization and Performance Estimation Knowing the source of delays in CMOS gates and being able to estimate them efficiently eliminates trial and error approach and saves time. In this chapter a back of the envelop approach is presented. The transistor is treated as a switch in series with a resistor (refer to page 104 of the course textbook). As a basis the inverter is designed to provide symmetric switching. This is achieved by sizing the p-type and n-type transistors so that they switch at the same rate. Double/triple the width of the p-type device to get Rn = Rp. Increasing the width of the devices by a factor k decreases the resistance by k while the capacitance increases. A three input NAND gate designed for worst case effective rise and fall times has the p-type devices’ widths doubled and those of the n-type devices tripplicated.

The Gate and Diffusion Capacitances For n-type devices designed for effective rise and fall time and stacked (placed in series) increase each device’s width by k, where k is the number of devices in the series chain. For the pMOS the stack of transistors must each be increased by 2k where k is the number of transistors in the stack. This knowledge allows you to estimate capacitances. Increasing the device width by k increases the capacitance by a factor k. Identifying the input and intrinsic parasitic capacitances of this gate. VDD 2C 2C 2C 2C 2C 2C 3C 3C 3C 3C 3C 3C

Identifying the Parasitic Capacitances For the gate shown, please determine the p- and n-type transistor widths based on the capacitance values shown. Provide an equivalent circuit showing the lumped capacitances (this is the example on page 161 of the course text). Capacitances for the Ground and VDD nodes have been excluded from the picture, why? Provide the time constant or propagation delay () for this gate The Elmore Delay Model is a first order delay approximation. If we view ON transistors as resistors we can represent a circuit as an RC ladder. The simple RC ladder network with one branch. R3 RN Vout R1 Vin R2 CN C1 C2 C3

The Elmore Delay Model Note that the capacitances are summed over all N while the resistors sum only up to the node of interest. If we assume a uniform RC ladder network consisting of identical elements R/N and C/N then the Elmore delay from input to the output becomes: We have already seen this equation and agreed that for N very large in a distributed RC model the previous expression reduces to If we consider a general RC network: With no resistor loops in the circuit, With all capacitors in the RC network connected between the node and ground and, That there is a unique resistive path from the input node to any other node in the cirrcuit.

The Elmore Delay Model (revisited) There is a unique resistive path from the input node to any other node in the circuit. Let Pi denote the unique path from the input node to the node I, where i=1, 2, 3, ….N. Refer to the lecture notes for an alternative representation. Let denote the portion of the path between the input and the node i, which is common to the path between the input and node j. If the input signal is a step pulse at time t=0, the Elmore delay at node i of the RC three is given by the expression: Consider node 7 on the RC tree shown and compute the delay from input to the node of interest.

The Elmore Delay Model (revisited) Note that R2, R3, R4, R5 and R8 are not in the common path from input node to node of interest. These resistors are thus excluded from the expression as per the formula and we still ask WHY? They surely would influence the delay, but it remember this is a first order approximation. The voltage drops across these resistors is not of paramount importance to the evaluation of the delay at node 7, but these node’s capacitances are. If you drop a significant amount of voltage across R3 for example that works in your favor as you might not have enough charge to effect any changes on C3. On the other hand if the resistance R3 is small the voltage drop is small as well implying that you will need to spend time charging/discharging capacitance C3. Including C3 becomes your worst case scenario and we thus have to include only the resistances in the common path.

The Linear Delay Model The Elmore delay allows us to view a circuit as an RC network and approximate delays. Another approach is that of using the logical effort. Here your primary concern would be to understand the terms propagation delay d stage effort f logical effort g electrical effort h (fan-out) These parameters describe activity for a single stage assuming that drive current is equivalent to that of a unit inverter. We said the logical effort g of a 2-input XOR (XNOR) is 4 and the struggle is to show how this value is obtained. Consider input A_bar (inverse of A), it drives both a p- and an n-type device. If we assume that we have a circuit (inverter) to generate A_bar then we have to compute G= gi for this case. Try determining that the logical effort for the XOR/XNOR is indeed 4 given this information. Understand how to estimate delays using both the Elmore delay model and the linear model.

Power Dissipation Knowledge of the critical path delays allows you to estimate the frequency at which your system can operate. Knowing the frequency could enable you to estimate dynamic power. We must know the three components of power, what causes them, how they are evaluated and how they can be minimized. The implications of technology scaling on power.