41 st DAC Tuesday Keynote

Giga-scale Integration for Tera-Ops Performance Opportunities and New Frontiers Pat Gelsinger Senior Vice President & CTO Intel Corporation June 8, 2004

Why Bother? G. Moore ISSCC 03 Litho Cost FAB Cost Based on SIA roadmap Test Capital

Scaling dead at 130-nm, says IBM technologist By Peter Clarke, Silicon Strategies May 04, 2004 (2:28 PM EDT) PRAGUE, Czech Republic — The traditional scaling of semiconductor manufacturing processes died somewhere between the 130- and 90-nanometer nodes, Bernie Meyerson, IBM's chief technology officer, told an industry forum. Why Bother? G. Moore ISSCC 03 Litho Cost FAB Cost

No exponential is forever, but you can delay forever… –Gordon Moore Believe in the Law $ per MIPS $ per Transistor

Direction For The Future

CMOS Outlook High Volume Manufacturing Technology Node (nm) Integration Capacity (BT) Moore’s Law Is Alive & Well … However …

CMOS Outlook High Volume Manufacturing Technology Node (nm) Integration Capacity (BT) Delay = CV/I scaling 0.7~0.7>0.7 Delay scaling will slow down Energy/Logic Op scaling >0.35>0.5>0.5 Energy scaling will slow down Bulk Planar CMOS High Probability Low Probability Alternate, 3G etc Low Probability High Probability Variability Medium High Very High ILD (K) ~3<3 Reduce slowly towards Reduce slowly towards RC Delay Metal Layers to 1 layer per generation

Guiding Observations Transistors (and silicon) are free Power is the only real limiter Optimizing for frequency AND/OR area may achieve neither

MOS Transistor Scaling GATESOURCE BODY DRAIN XjXjXjXj T ox D GATE SOURCE DRAIN L eff BODY Dimensions scale down by 30% Doubles transistor density Oxide thickness scales down Faster transistor, higher performance V dd & V t scaling Lower active power Technology has scaled well, and will continue…

Delivering Performance in Power Envelope Mobile, Power Envelope ~20-30W Desktop, Power Envelope ~60-90W Server, Power Envelope ~ W

Strained Silicon – 90nm+ D G S S D G Tensile Si 3 N 4 Cap SiGe S-D creates strain 10-25% higher ON current 84-97% leakage current reduction 84-97% leakage current reductionOR 15% active power reduction 15% active power reduction PMOS NMOS Source: Mark Bohr, Intel

Gate & Source-Drain Leakage Gate Leakage Solutions: High-K + Metal Gate 90nm MOS Transistor50nm Silicon substrate 1.2 nm SiO 2 Gate

New Transistors: Tri-Gate… Tri-gate W Si LgLg T Si Gate 1 Gate 2 Gate 3 Source Drain Improved short-channel effects Higher ON current for lower SD Leakage Manufacturing control: research underway Source Drain Gate Source: Intel

Metal Interconnects Interconnect RC Delay

New Challenge: Variations Static & Dynamic

Random Dopant Fluctuations UniformNon-uniform

Sub-wavelength Lithography Adds Variations 193nm 248nm 365nm LithographyWavelength 65nm 90nm 130nm Generation Gap 45nm 32nm 13nm EUV 180nm

Impact of Static Variations 130nm 30% 5X Frequency~30%LeakagePower~5-10X Normalized Leakage (Isb) Normalized Frequency

Dynamic Variations: V dd & Temperature Heat Flux (W/cm 2 ) Results in V cc variation Temperature Variation (°C) Hot spots

Technology Challenges Power: Active + Leakage Interconnects (RC Delay) Variations

Design Methodology Is Changing…

Active Power Reduction SlowFastSlow Low Supply Voltage High Supply Voltage Multiple V dd V dd scaling will slow downV dd scaling will slow down Mimic V dd scaling with multiple V ddMimic V dd scaling with multiple V dd Challenges:Challenges: –Interface between low & high V dd –Delivery and distribution

Leakage Control Body Bias V dd V bp V bn -V e +V e 2-10XReduction Sleep Transistor Logic Block XReduction Stack Effect Equal Loading 5-10XReduction

Adaptive Body Biasing Number of dies Frequency too slow f target too leaky f target FBB RBB Frequency f f ABB FBB RBB

Adaptive Body Biasing 0% 20% 60% 100% Accepted Die No BB 100% yield ABB High Frequency Bin Low Frequency Bin 97% highest bin Within die ABB 97% highest freq bin with ABB for within die variability 100% yield with Adaptive Body Biasing

RC Delay Mitigation Logic Block Freq = 1 V dd = 1 Throughput = 1 Power= 1 Area = 1 Power Den = 1 V dd Logic Block Freq = 0.5 V dd = 0.5 Throughput = 1 Power = 0.25 Area = 2 Power Den = V dd /2 Logic Block Throughput Oriented Design RC Delay Tolerant Design Lower Power And Power Density

Variation Tolerant Circuit Design Low-V t usage low high Higher probability of target frequency with: 1.Larger transistor sizes 2.Higher Low-V t usage But with power penalty But with power penalty Transistor size small largepower target frequency probability

µ-architecture Is Also Changing…

Variations and µ-architecture # of critical paths Mean clock frequency Clock frequency Number of dies 0% 20% 40% 60% # critical paths 0% 20% 40% -16%-8%0%8%16% Delay 20% 40% NMOS PMOS Device I ON # of samples (%) Variation (%) Logic depth Ratio of delay-  to Ion-  to Ion-  16 49

Logic depth Large Small frequency target frequency probability Variation Tolerant µ-architecture Decrease variability in the design: 1.Deeper logic depth 2.Smaller number of critical paths # uArch critical paths MoreLess

Implications For CAD Logic & Circuits Layout Test

Leakage Power FrequencyDeterministicProbabilistic 10X variation ~50% total power Probabilistic Design Delay Path Delay Probability Deterministic design techniques inadequate in the future Due to variations in: V dd, V t, and Temp Delay Target # of Paths Deterministic Delay Target # of Paths Probabilistic

Shift in Design Paradigm Multi-variable design optimization for:Multi-variable design optimization for: – Yield and bin splits – Parameter variations – Active and leakage power – Performance Tomorrow: Global Optimization Multi-variateToday: Local Optimization Single Variable

Today’s Freelance Layout V ss V dd OpOp IpIp V ss V dd OpOp No layout restrictions

Future Transistor Orientation Restrictions V ss V dd OpOp IpIp V ss V dd OpOp Transistor orientation restricted to improve manufacturing control

OpOp V ss V dd IpIp V ss V dd OpOp Future Transistor Width Quantization

Today’s Unrestricted Routing

Future Metal Restrictions

Today’s Metric: Maximizing Transistor Density Dense layout causes hot-spots

Tomorrow’s Metric: Optimizing Transistor & Power Density Balanced Layout

Other Challenges … Test & Debug

Test Challenges Based on SIA roadmap Test Capital Understandable … Based on SIA roadmap Test Capital/ Transistor Disturbing …

On Die Test Methodology ISSCC 2003: 8Gb/s Differential Simultaneous Bidirectional Link with 4mV, 9ps Waveform Capture Diagnostic Capability <1E-8 1E-7 1E-6 1E-5 >1E Time (ps) Voltage (V) Time (ns) Differential Voltage (V) On-Die Scope Waveform Move from external to on-die “self testing”Move from external to on-die “self testing” High-speed test & debug hardware on each dieHigh-speed test & debug hardware on each die Low speed, low cost, interface to external testerLow speed, low cost, interface to external tester On die debug & test of 8Gb/sec IO interface

Other Challenges … System-level Design Mixed-signal Design System-level Design Correctness Correctness Multi-clock domains Multi-clock domains Resiliency Resiliency

Business As Usual Is NOT An Option For CAD…

Summary CMOS scaling will continue, transistors become free Deterministic  Probabilistic, Single  Multi local to global optimization: power,… BELIEVE SHIFT EMBRACE