1 U NIVERSITY OF M ICHIGAN 11 1 SODA: A Low-power Architecture For Software Radio Author: Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scott Mahlke, Trevor Mudge Advanced Computer Architecture Laboratory University of Michigan at Ann Arbor Chaitali Chakrabarti Department of Electrical Engineering Arizona State University Kriszti´an Flautner ARM, Ltd. Presenter: Wei Miao Jingcheng Wang

2 U NIVERSITY OF M ICHIGAN Overview  Introduction on SDR  Behavior model and Design tradeoff  Architecture analysis  Performance analysis  Summary

3 U NIVERSITY OF M ICHIGAN INTRODUCTION AND ANALYSIS Wei Miao

4 U NIVERSITY OF M ICHIGAN Basic introduction on SODA  Signal-processing On-Demand Architecture  Support software radio  4-core, containing asymmetric pipeline  Meet requirement of 2Mbps WCDMA/24Mbps a

5 U NIVERSITY OF M ICHIGAN Introduction on SDR  Software Defined Radio(SDR)  Decode different signals on a single processor

6 U NIVERSITY OF M ICHIGAN Why SDR?  Easy to implement & update  Multi-mode operation  Prototyping and bug fixes  Shorter time to develop (Picture From Lin, ISCA’06 slides)

7 U NIVERSITY OF M ICHIGAN Challenges of SDR  Need to achieve high throughput  Power limitation

8 U NIVERSITY OF M ICHIGAN Wireless protocols behavior  Feed-forward, multiple kernel  Low but heterogeneous requirement for inter-kernel communication  Real-time deadline  Heavy data parallelism  8-16 bits data width  Scalar vector operation

9 U NIVERSITY OF M ICHIGAN Design Tradeoff  Concurrent execution vs. Single Context execution  Static Multi-core Scheduling vs. Multi-threading  Vector vs. SIMD vs. VLIW

10 U NIVERSITY OF M ICHIGAN SODA ARCHITECTURE AND RESULTS Jingcheng Wang

11 U NIVERSITY OF M ICHIGAN  4 PEs  static kernel mapping and scheduling  SIMD+Scalar units  1 ARM GPP controller  scalar algorithms and protocol controls SODA System Architecture (From Lin, ISCA’06 slides)

12 U NIVERSITY OF M ICHIGAN SODA PE Architecture (From Lin, ISCA’06 slides)

13 U NIVERSITY OF M ICHIGAN SODA PE Scalar Pipeline (From Lin, ISCA’06 slides)

14 U NIVERSITY OF M ICHIGAN SODA PE SIMD Pipeline (From Lin, ISCA’06 slides)

15 U NIVERSITY OF M ICHIGAN SODA PE SIMD Pipeline (From Lin, ISCA’06 slides)

16 U NIVERSITY OF M ICHIGAN SODA PE SIMD Shuffle Network (From Lin, ISCA’06 slides)

17 U NIVERSITY OF M ICHIGAN W-CDMA Mapping On SODA (From Lin, ISCA’06 slides)

18 U NIVERSITY OF M ICHIGAN

19 U NIVERSITY OF M ICHIGAN SIMD Design and Tradeoffs  40GOPS required  In 4 PE system, 10 GOPS in each

20 U NIVERSITY OF M ICHIGAN Low-power Design  Clustered Register Files with 2 Read Ports and 1 Write Port  Fewer Memory Read/Write Ports  Smaller Instruction Fetch logic

21 U NIVERSITY OF M ICHIGAN Experiment Methodology  Area and power estimation calculated using RTL Verilog model  Synthesized using Synopsys Physical Compiler and TSMC 180nm Library  Memories generated by Artisan SRAM generator  Estimated 90nm and 65nm processes using a quadratic scaling factor  Dynamic power was estimated from behavior simulation on their system simulator  Leakage power was estimated at 30% of the total power

22 U NIVERSITY OF M ICHIGAN Performance results

23 U NIVERSITY OF M ICHIGAN Power Area result  Typical cellular phone power for physical layer ~ 200mW

24 U NIVERSITY OF M ICHIGAN Discussion Points  1. The author only synthesized the core in TSMC180nm and estimated the area and power of 90nm and 65nm. Is that fair to claim that the architecture meet the requirement?  The author claims that he reduces CDMA search algorithm from 26.5Gops in GP processor to 200Mops in SODA. And the main reason is due to SIMD execution. Is SIMD the only and main speedup factor? Is the novelty of paper enough?  2. Utilization of the 4 PEs are 60%, 50%, 100% and 94% respectively. Can it do better?

25 U NIVERSITY OF M ICHIGAN Reference   3&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F1089 9%2F34298%2F pdf%3Farnumber%3D &url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F1089 9%2F34298%2F pdf%3Farnumber%3D