In God We Trust Class presentation for the course: “Custom Implementation of DSP systems” Presented by: Mohammad Haji Seyed Javadi May 2013 Instructor:

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Presentation transcript:

In God We Trust Class presentation for the course: “Custom Implementation of DSP systems” Presented by: Mohammad Haji Seyed Javadi May 2013 Instructor: Prof. S.M. Fakhraei This presentation is mainly based on : M. Mehendale, et. al., “A true multistandard, programmable, low-power, full HD video-codec engine for smart phone SoC”, ISSCC, page IEEE, 2012 All the materials are copyrights of their respective authors as listed in references ECE Department, University of Tehran

Outline Video-codec concepts H.264 codec data flow Related implementations of video codec. IVA-HD architecture IVA-HD configurability OMAP4 architecture IVA-HD physical properties Comparison with previous works 2

Video-Codec[1,2] CODE + DECODE ==> CODEC Application samples Camcorder Video conferencing Smart phone Various Standards MPEG-1, MPEG-2, H.263, H.264 Concerning implementation issues Higher quality Lower power consumption Area efficiency 3

As a sample: H.264/AVC H.264 video-codec block diagram [1] 4

Related works Low power video-codecs[4-6] Using single codec optimized circuitry Massive parallelism Lower voltage and frequency Drawbacks: Targeted to a specific standard Address either encode or decode Not area efficient to support multiple video standards 5

Related works (Cont’d) Multicore programmable processor[7] Support multiple standards Eight media processing engine (MPEs) Each MPE consists of RISC processor and co-processor Drawbacks: Not scalable to meet full HD performance Inefficient in terms of area and power 6

Related works (Cont’d) Application processor[8] Decoupling stream processing and pixel processing Using 2 macro block pipelining Low power consumption (342 mW) Drawbacks: Introduce a frame delay  higher latency Can not support fixed bitrate encoding 7

IVA-HD: Multi-standard video coding engine[3] Asynchronous Configurable pipeline Distributed control 6 hardware accelerators IVA-HD architecture [3] 8

IVA-HD Configurability[3] IVA-HD programmability/configurability to support various use cases[3] 9

OMAP-4 Application Processor OMAP-4 functional diagram[3] OMAP44x block diagram[9] 10

IVA-HD Physical Properties[3] 45-nm CMOS process Clock frequency for H MHz (1080 P, 30 FPS) Power management techniques DVFS, AVS and ABB Supply Voltage 1.1 V + AVS adjusted H. 264 HP decode power Range from 65 to 95 mW H. 264 HP encode power Range from 100 to 145 mW Occupies less than 10 % of OMAP 4 chip area OMAP-4 chip micrograph[3] 11

Comparison table[3] Comparison with previous works [3] 12

References [1] Iain E. G. Richardson, “H.264 and MPEG-4 Video compression”, Wiley press [2] T. Wiegand, et. al., “Overview of the H.264/AVC Video Coding Standard”, IEEE TCSVT, Vol.13, No. 7, pp , [3] M. Mehendale, et. al., “A true multistandard, programmable, low-power, full HD video-codec engine for smart phone SoC”, IEEE ISSCC, pp , [4] D. Finchelstein, et al., “A Low-Power 0.7-V H p Video Decoder”, ISSCC, pp , April, [5] Y. Lin, et al., “A 242mW 10mm2 1080P H.264/AVC High-Profile EncoderChip”, ISSCC Dig. Tech. Papers, pp , Feb [6] Y. Kikuchi, “A 222mW H.264 Full-HD Decoding Application Processor with x512b Stacked DRAM in 40nm”, ISSCC Dig. Tech Papers, pp , Feb [7] S. Nomura, et al., “A 9.7mW AAC-Decoding, 620mW H p 60fpsDecoding, 8-Core Media Processor with Embedded Forward-Body-Biasing andPower-Gating Circuit in 65nm CMOS Technology”, ISSCC Dig. Tech Papers, pp , Feb [8] K. Iwata, et al., “A 342mW Mobile Application Processor with Full-HD Multi-Standard Video Codec”, ISSCC Dig. Tech. Papers, pp , Feb [9] 13