Transactional Memory Overview Olatunji Ruwase Fall 2007 Oct

Future PCs are Multicore

Parallel s/w for performance Locks Deadlocks Priority Inversion Buggy Convoy Effect Limited concurrency

Transactions Borrowed from Databases Definition : A transaction is a finite sequence of machine instructions executed by a single process, that satisfies the following properties Atomicity Serializability Herlihy and Moss. “Transactional Memory: Architectural Support for Lock-free Data Structures, ISCA’93

How transactions work Make private copy of shared data Make updates on private copy If shared data is unchanged Update shared data with private copy Else conflict has occurred Discard private copy and repeat transaction

Requirements for supporting transactions Buffering Conflict detection Abort/Rollback Commit

Transactional Memory Herlihy and Moss, ISCA ’93 ISA changes LT,LTX, ST, COMMIT, VALIDATE, ABORT Fully associative transactional cache Per processor Contents are exclusive of regular cache Cache coherence protocol changes Transactional cache line states Transactional bus messages Snoopy bus based implementation

TM support for transactions BufferingTransactional cache Conflict detectionCache coherence protocol Abort/RecoveryInvalidate transactional cache line CommitValidate transactional cache line

Transactional Cache Fully set associative cache Each cache line can be in only one of transactional or regular cache Holds transactional writes Transactional writes are hidden from other processors and memory Makes updated lines available for snooping on COMMIT Invalidate updated line on ABORT

Herlihy and Moss, ISCA ‘93 M S S XCommit XAbort CacheTransaction Cache CPU Memory

Sample Counter code

Exposing more concurrency Doubly linked list implementation of queue Head, Tail pointers If queue not empty Only head pointer is used for dequeuing Only tail pointer is used for enqueuing Concurrent enqueuing/dequeuing Possible in TM Not possible with locks

Challenges of TM Long transactions I/O Nested transactions Interrupts

Other TM Ideas Speculative Lock Elision Software Transactional Memory Requires no hardware changes Allows composition of transactions

Speculative Lock Elision Ravi and Goodman, MICRO ‘01 Speculatively remove lock acquire and removal instructions Microarchitectural changes No changes to cache systems No changes to ISA Can work with existing lock based code

SLE example

Credits for slides Bryant Lee (CMU) Transactional Memory: Principles and Current Research Colin Blundell (UPenn) Transaction Memory Overview Kevin Moore (UW) Thread-Level Transactional Memory

Compare TM and TLS TM is optimistic synchronization TLS is optimistic parallelization Any other similarities or differences

Questions/Discussions