Self-Checking Circuits Delay-Insensitive Codes and Self-Checking Checkers

Self-Checking Circuits Most important factors in designing a digital system: Speed, Cost and Correctness. Some systems used in 1. medical equipment used in ICUs, 2. aircraft control systems, 3. nuclear reactor control systems, 4. military systems and 5. computing systems used in space missions. High reliability is of the utmost importance. DSM technology: Signal Integrity problem

Self-Checking Circuits Def: Self-Checking Circuit Circuits detecting faults in normal operation. Testing vs self-checking? Faults: stuck at zero and stuck at one stuck at one in one input of an 2-input OR gate? stuck at zero in one input of an 2-input OR gate? stuck at one in one input of an 2-input AND gate? stuck at zero in one input of an 2-input AND gate?

Self-Checking Circuits: Def: Error An incorrect output caused by a stuck-at fault. Def: Single Error An error that affects only a single component value Def: Multiple Error An error that affects multiple component values. The component value affected by an error may change form 0 to 1, or vice versa. Def: unidirectional errors When all components affected by a multiple error change their values monotonically.

Self-Checking Circuits: Def: Error Detecting Code Def: Hamming distance of two vectors x and y the number of components in which they differ. Def: Hamming distance of a code X the minimum of the Hamming distances between all possible pairs of code words in X.

Self-Checking Circuits: Lemma: A code with Hamming distance d+1 can detect all errors with weight d or less. Lemma: A code with Hamming distance 2c+1 can correct all errors with weight c or less. One-Hot Code: 1. Delay-Insensitive Code 2. Detect one error (H.D.=2).

Fault-tolerant Systems: masking scheme: 1. All of the redundant modules are active at all times. 2. When a fault occurs, the faulty module is masked. 3. The most common masking scheme is triple modular redundancy in which the outputs of three copies of function units are fed to a majority gate. 4. If one of the three modules becomes faulty, the two remaining fault-free modules mask the results of the faulty one when the majority vote is performed.

Fault-tolerant Systems: Standby scheme: 1. only one copy of the system is active. 2. When the active module detects the occurrence of faults, the standby module is activated and takes over the control. 3. Thus, to use self-checking circuits in a fault-tolerant system, double module redundancy is sufficient. 4. This scheme may be superior than the former in terms of power consumption and hardware cost.

Self-checking scheme Self-Checking scheme: 1. a self-checking functional unit. 2. a self-checking checker. Self-Checking functional unit Inputs X Outputs Y ... ... ... ... Self-checking checker X: input code space Y: output code space Error signal

Self-Checking Circuits During the fault-free operation: a normal input will produce a normal output. If an incorrect output is produced due to a fault, the error should be detected by the self-checking checker.

Self-checking scheme

Self-checking scheme Fault Secure(FS): code word input to a faulty circuit must not produce an incorrect code word output. Self-testing: a fault in a circuit must be detected by some input.

Self-checking scheme Fault Secure(FS): Self-testing:

Self-checking scheme Totally Self-Checking: Partially Self-Checking:

Self-checking scheme Fault-secure-only circuits: 1. No erroneous results go undetected. 2. However, it is possible that some fault can never be detected. Self-testing-only circuit: 1. Any fault can produce undetected errors for a short time. 2. However, there is a code word input that can detect the fault.

Self-checking scheme Totally self-checking circuit: 1. no erroneous results go undetected and 2. any fault will be eventually detected. Partially self-checking circuits: 1. This approach is to restrict the set of faults for which the circuit has to be checked. 2. They are introduced to provide low-cost error detection. 3. They may be used in non-critical applications.

Delay-Insensitive Tree Adder

Self-Checking Checkers Code-disjoint: TSC Checker: With the code-disjoint feature, one may be able to test if the TSC checker is malfunction.

DI Adder Checker Code word input: one-hot code of output signals Correct code word output Z0 Z1 = 10 Incorrect code word outputs Z0 Z1 = {00 01 11}

Delay-Insensitive Codes M/N code (M<N): M-out-of-N code all valid code words have exactly M 1’s and N-M O’s. Length of M/N code: C(N,M) 1. One-hot code(1/N code): a. dual-rail encoding: (01 10) b. 1/3 code: (001 010 100) c. length of one-hot code: C(N,1) 2. Optimal M/N code: M=N/2 a. 3/6 code: (000111,001011,001101,001110, …) b. length of M/N Code = C(N, N/2) Berger Code, Modified Berger code:

Delay-Insensitive Transmission Sender Receiver I I DI codes decoder encoder

Delay-Insensitive Transmission Cost factors: Number of Wires (cost) Encoder (logic complexity/computation time) Decoder (logic complexity/computation time)

Delay-Insensitive Codes: Berger Berger Code: 1. Systematic code: Information bits + Check bits (note that M/N code is a nonsystematic code). 2. 3. Check bits = counting the number of 0’s in I bits. 4. See table (Next page)

Delay-Insensitive Codes

Delay-Insensitive Transmission: Berger codes DI codes Sender Receiver I’ I Check bits C’’ C C’ Check bits Compare Valid?

Self-Checking Checkers: Self-checking Checkers of M/N code 1. One-hot code(1/N code): a. dual-rail encoding: (01 10): shown in DI Adders b. 1/N code: c. Z0: completion signal Z1: error detection C(N,2) ... & & & ... + + Z1 Z0

Self-Checking Checkers: Self-checking Checkers of M/N code 2. Optimal M/N code: M=N/2 a. 3/6 code: (000111,001011,001101,001110, …) b. length of M/N Code = C(N, N/2) N/2 C(N,N/2) N/2+1 C(N,n/2+1) .. .. ... ... & & & & & & + + Z0 Z1

Self-Checking Checkers: Use Sorting Networks for Self-checking Checkers: General sorting network: A1 An Sorting Network Max(A1, … , An) Min(A1, … , An) n unsorted numbers n sorted numbers ... ... A1 A2 Max(A1,A2) Min(A1, A2) Comparator

Self-Checking Checkers: Binary sorting network: x1 xn Sorting Network 1 k 1’s 1 0 n-k o’s n binary input ... ... ... x1 x2 Max(x1,x2)= x1+x2 Min(x1, x2)= x1x2 Comparator

Self-Checking Checkers: Binary sorting network for 2/4 code CMP CMP CMP CMP CMP

Error Collection Codes: Code with HD>=3 may correct error Ex. HD=4: 0011 1100