DSD 2007 Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs Andrzej Krasniewski Institute of Telecommunications WARSAW UNIVERSITY OF TECHNOLOGY

CED for FSMs Designed for Implementation with EMBs of FPGAs - 2 DSD’07A.Krasniewski Why CED for FSMs implemented with SRAM-based FPGAs?  configuration memory - susceptible to transient faults  embedded memory (major component of FSMs) - more susceptible to transient faults than logic  architectural features of FPGAs with embedded memory make CED relatively inexpensive Earlier proposed techniques, intended for FSMs implemented with gates and FFs (standard cells) - unsuitable GOAL Develop a low-cost CED scheme for FSMs implemented using embedded memory of FPGAs Motivation

CED for FSMs Designed for Implementation with EMBs of FPGAs - 3 DSD’07A.Krasniewski  Implementation of FSMs using FPGAs with embedded memory  Concurrent error detection - architecture - effectiveness of fault detection - overhead  Conclusion OUTLINE

CED for FSMs Designed for Implementation with EMBs of FPGAs - 4 DSD’07A.Krasniewski  Implementation of FSMs using FPGAs with embedded memory  Concurrent error detection - architecture - effectiveness of fault detection - overhead  Conclusion OUTLINE

CED for FSMs Designed for Implementation with EMBs of FPGAs - 5 DSD’07A.Krasniewski IOEs DSP block LABs M4K RAM block LABs M-RAM block M512 RAM block Altera Stratix Embedded memory in FPGAs - Example

CED for FSMs Designed for Implementation with EMBs of FPGAs - 6 DSD’07A.Krasniewski read/write memory modules RAM FIFO shift registers read-only memory modules (ROMs) implementation of combinational logic implementation of sequential logic (FSMs) Embedded memory in FPGAs - Applications

CED for FSMs Designed for Implementation with EMBs of FPGAs - 7 DSD’07A.Krasniewski ROM m+p ADDRESS REGISTER p n m address output input SIMPLE STRUCTURE entire combinational logic located in memory (ROM) ROM-based FSM design next state w w < m+p ADDRESS MODIFIER (gates) ADDRESS REGISTER p n m address output input EXTENDED STRUCTURE next state ROM limited applicability – requires large memory

CED for FSMs Designed for Implementation with EMBs of FPGAs - 8 DSD’07A.Krasniewski Embedded Memory LUTs in PLBs (Xilinx CLBs, Altera LEs) ADDRESS REGISTER address output input next state ROM FSM design for FPGA with embedded mem. CED scheme in [DFT’04] ADDRESS MODIFIER flip-flops in PLBs (internal register of Emb Mem)

CED for FSMs Designed for Implementation with EMBs of FPGAs - 9 DSD’07A.Krasniewski Embedded Memory ADDRESS REGISTER address output input next state ROM flip-flops in PLBs (internal register of Emb Mem) FSM design for FPGA with embedded mem. Embedded Memory studies in synthesis of FPGA-based circuits new CED scheme ADDRESS MODIFIER

CED for FSMs Designed for Implementation with EMBs of FPGAs - 10 DSD’07A.Krasniewski ADDRESS REGISTER embedded memory input X next state Q memory H FSM design for FPGA with embedded mem. memory G ADDRESS MODIFIER clock A1A2A2 „ROM” Qa, Qb Xa, Xb embedded memory programmable logic components Xb, XcQb, Qc output Y input X, next state Q group a → Addr Reg group b → Addr Reg & Mem G group c → Mem G

CED for FSMs Designed for Implementation with EMBs of FPGAs - 11 DSD’07A.Krasniewski  Implementation of FSMs using FPGAs with embedded memory  Concurrent error detection - architecture - effectiveness of fault detection - overhead  Conclusion OUTLINE

CED for FSMs Designed for Implementation with EMBs of FPGAs - 12 DSD’07A.Krasniewski GOAL: low-cost solution Assumptions ADDR REG address output input next state memory H („ROM”) memory G (ADDR MOD) CED scheme:  can add to the width of the mem. word  cannot add to the width of mem. address state encoded with a minimal no. of bits earlier proposed CED techniques for sequential circuits (based on state encoding with EDC) - not applicable one extra bit of address → size of the required memory doubles address space of EMBs - quite limited (address  13 bits) width of the embedded memory word can be extended significantly with no impact on the performance (speed) of the circuit

CED for FSMs Designed for Implementation with EMBs of FPGAs - 13 DSD’07A.Krasniewski INPUT clock XapQab’ address A ADDRESS REGISTER ADDRESS PARITY CHECKER ERR4OUTPUT ERR2 XbQaQbA2 A1 AUXILIARY CHECKER next state OUTPUT PARITY CHECKER ADDRESS MODIFIER pXab’ Qb + pQab + ’pAQc + Qa + pYpQc + ’LY pXQcpA2’A2 pXQcpA2’pXc’pQc’ pXab’XaXbXcpXc’ „ROM” ERR1 ERR3 Proposed CED scheme

CED for FSMs Designed for Implementation with EMBs of FPGAs - 14 DSD’07A.Krasniewski Error detection mechanisms ERR1 parity checking for address to memory H ERR2 parity checking for data feeding memory G only ERR3 parity checking for output ERR4 checking for address legality (optional) Checkers implemented with PLBs (outputs – in two-rail code)

CED for FSMs Designed for Implementation with EMBs of FPGAs - 15 DSD’07A.Krasniewski INPUT clock XapQab’ address A ADDRESS REGISTER ADDRESS PARITY CHECKER ERR4OUTPUT ERR2 XbQaQbA2 A1 AUXILIARY CHECKER next state OUTPUT PARITY CHECKER ADDRESS MODIFIER pXab’ Qb + pQab + ’pAQc + Qa + pYpQc + ’LY pXQcpA2’A2 pXQcpA2’pXc’pQc’ pXab’XaXbXcpXc’ „ROM” ERR1 ERR3 parity checking for address to memory H

CED for FSMs Designed for Implementation with EMBs of FPGAs - 16 DSD’07A.Krasniewski INPUT clock XapQab’ address A ADDRESS REGISTER ADDRESS PARITY CHECKER ERR4OUTPUT ERR2 XbQaQbA2 A1 AUXILIARY CHECKER next state OUTPUT PARITY CHECKER ADDRESS MODIFIER pXab’ Qb + pQab + ’pAQc + Qa + pYpQc + ’LY pXQcpA2’A2 pXQcpA2’pXc’pQc’ pXab’XaXbXcpXc’ „ROM” ERR1 ERR3 parity checking for data feeding memory G only

CED for FSMs Designed for Implementation with EMBs of FPGAs - 17 DSD’07A.Krasniewski INPUT clock XapQab’ address A ADDRESS REGISTER ADDRESS PARITY CHECKER ERR4OUTPUT ERR2 XbQaQbA2 A1 AUXILIARY CHECKER next state OUTPUT PARITY CHECKER ADDRESS MODIFIER pXab’ Qb + pQab + ’pAQc + Qa + pYpQc + ’LY pXQcpA2’A2 pXQcpA2’pXc’pQc’ pXab’XaXbXcpXc’ „ROM” ERR1 ERR3 parity checking for output

CED for FSMs Designed for Implementation with EMBs of FPGAs - 18 DSD’07A.Krasniewski INPUT clock XapQab’ address A ADDRESS REGISTER ADDRESS PARITY CHECKER ERR4OUTPUT ERR2 XbQaQbA2 A1 AUXILIARY CHECKER next state OUTPUT PARITY CHECKER ADDRESS MODIFIER pXab’ Qb + pQab + ’pAQc + Qa + pYpQc + ’LY pXQcpA2’A2 pXQcpA2’pXc’pQc’ pXab’XaXbXcpXc’ „ROM” ERR1 ERR3 checking for address legality

CED for FSMs Designed for Implementation with EMBs of FPGAs - 19 DSD’07A.Krasniewski in fault-free operation some state-input combinations never occur (in address register) illegal address illegal address illegal state code Legality of address

CED for FSMs Designed for Implementation with EMBs of FPGAs - 20 DSD’07A.Krasniewski  Implementation of FSMs using FPGAs with embedded memory  Concurrent error detection - architecture - effectiveness of fault detection - overhead  Conclusion OUTLINE

CED for FSMs Designed for Implementation with EMBs of FPGAs - 21 DSD’07A.Krasniewski Target faults permanent or transient faults (in particular, SEU-induced) associated with a single input or output of any component that result in an incorrect state or output of the circuit THEOREM The proposed CED scheme guarantees the detection of each target fault, provided that two different transient faults do not occur in two consecutive clock cycles. Faults are detected with no latency (no later than in the cycle in which an incorrect state is present in the address register). Proof: by examining all possible fault classes the feature not provided by a majority (if not all) of earlier CED techniques Note: detection of faults in input X Effectiveness of fault detection Address legality checking – optional enhances detectability of multiple faults

CED for FSMs Designed for Implementation with EMBs of FPGAs - 22 DSD’07A.Krasniewski  Implementation of FSMs using FPGAs with embedded memory  Concurrent error detection - architecture - effectiveness of fault detection - overhead  Conclusion OUTLINE

CED for FSMs Designed for Implementation with EMBs of FPGAs - 23 DSD’07A.Krasniewski  EMBs of different size: K bits with configurable data width: 1, 2, 4, 8, or 16 bits for 4K EMBs: Altera APEX II, Stratix Xilinx Virtex, Virtex-E, Spartan II  no extension of max EMB address space Cost (overhead) – Experimental study proprietary tool FSMdec [BoFL07] ‘original’ circuit synthesis of FSM for EMB-based implementation circuit with CED design of CED scheme evaluation of overhead

CED for FSMs Designed for Implementation with EMBs of FPGAs - 24 DSD’07A.Krasniewski  2 parity bits associated with circuit input  extension of mem G word by 2* bits  extension of mem H word by 4*(5*) bits  extension of address register by 6* bits  address and auxiliary parity checkers  output parity checker circuit independent circuit dependent EXTRA LOGIC Cost (overhead) * fewer in some cases extra PLBs extra EMBs logic cell = 4-input LUT + FF 10 extra logic cells = 1 extra EMB of 1K

CED for FSMs Designed for Implementation with EMBs of FPGAs - 25 DSD’07A.Krasniewski average overhead = 27.2% Cost (overhead) – Experimental results

CED for FSMs Designed for Implementation with EMBs of FPGAs - 26 DSD’07A.Krasniewski difficult to draw conclusions, but... intended for FSMs implemented with standard cells Cost (overhead) estimation – comparison

CED for FSMs Designed for Implementation with EMBs of FPGAs - 27 DSD’07A.Krasniewski  Implementation of FSMs using FPGAs with embedded memory  Concurrent error detection - architecture - effectiveness of fault detection - overhead  Conclusion OUTLINE

CED for FSMs Designed for Implementation with EMBs of FPGAs - 28 DSD’07A.Krasniewski  detection of all permanent and transient faults associated with single in/out of components  no latency  low-cost average overhead < 30% CED scheme for an FSM implemented using an FPGA with embedded memory Conclusion

CED for FSMs Designed for Implementation with EMBs of FPGAs - 29 DSD’07A.Krasniewski