JEDA Technologies, Inc. Verification Methodologies in a TLM-to-RTL Design Flow Atsushi Kasuya.

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Presentation transcript:

JEDA Technologies, Inc. Verification Methodologies in a TLM-to-RTL Design Flow Atsushi Kasuya

Agenda Introduction Cycle Accurate Temporal Assertion OCP Compliance Checker Assertion on PVT Model OCP TL2 PVT Example Assertion on PV Model PV Transaction Level Assertion Example Assertion Reuse Conclusion and Future Work

Introduction Native SystemC Assertion (NSCa) Temporal Assertion Written Natively in SystemC context Cycle Accurate Temporal Primitives (like SVA/PSL) PVT level Assertion Primitives PV level Assertion Primitives (under development) Two ways to write assertion NSC syntax ( Extended C++ syntax to handle assertion construct natively. = one to five cycle delay) Assertion Macros Temporal Expression as a regular C expression Support assertions for models in various abstraction levels

Assertion Hierarchy Functional Level Functional Level Protocol Level Protocol Level Physical Level Physical Level Master DeviceSlave Device PV TLA PVT TLA CLA

Cycle Accurate Temporal Assertion SVA/PSL like temporal primitives always imply ( |->, |=> ) m to n delay ) repetitions ( [*m:n], [->m:n], [=m:n] ) and, or, intersect, within, throughout, etc. Native in SystemC thread context Provides a boolean expression in C++ code if ( !nsc_sequence( [1,5] gnt.read()==1 ) ) error() ; if (!NSC_SEQUENCE( NSC_BOOL(req.read()==1) && NSC_SEQ(1,5, NSC_BOOl(gnt.read()==1)) ) ) error() ;

OCP Protocol Checker OCP 2.2 Compliance Checker Library Written with NSCa Cycle Accurate Assertion On-the-Fly Check as simulation runs Based on the OCP-IP Functional Verification Working Group (FVWG) compliance check specification Implemented all of the compliance checks (70+ checks) OCP MasterOCP Slave OCP TL1 Channel Config File OCP Monitor NSCa OCP Compliance Checker

PVT Level Assertion Aimed to provide high level performance check Event Driven Checker Simple Temporal Primitives Asynchronous Event Handling Mutex Primitive C++ Class Library ( User Extendable ) Queue Models Coverage Bin Unified Verification Error Handling to support debugging in GUI

PVT Assertion Example Outstanding Request Monitor Simply connect the specific events to a queue model Request Transactions Response ReqEnd ResponseStart always ReqEnd ResponseStart Simple Queue (outstanding req counting) arrive depart Coverage Bin (outstanding req coverage) Property Mutex

PV Level Assertion Aimed to provide high level protocol check Callback Driven Checker Support 0-Delay Model New Set of PV Temporal Primitives Construct temporal sequence without clock Interface to Callback Events Callback Layer is isolated from the Assertion itself Can be connected to various if (e.g. TLM 2.0 Analysis Port) Re-use assertions over different abstract models

PV Level Assertion Primitives Primitives works without Clock A sequence is constructed with Callback events and TLA primitives Property Primitives tla_always( ) always check the given sequence tla_alwaysif( ) tla_then( ) when seqence1 occurs then check sequence2 Sequence Primitives tla_repeat( N, ) repeat sequence N times ( ) tla_within ( ) seqence1 must happen within sequence2 ( ) tla_without ( ) seqence1 must not happen within sequence2

PV Level Assertion Primitives (Cnt.) Sequence Primitives (Continued) ( M, ) tla_followedby ( N, ) seqence1 must be followed by sequence2 M: number of times (-1 means endless) N: number of outstanding sequence1 before sequence2 is detected ( ) tla_until ( ) repeatedly check seqence1 until sequence2 occurs tla_cositch ( tla_case( ) tla_then ( ).. ) tla_end Concurrent swich, when seqence1 happens, check sequence2

PV Level Assertion Example When Register A is accessed, Register B must be accessed before the next Register A access tla_always( (-1, REG_A_ACCESS() ) tla_followedby( 0, REG_B_ACCESS() ) ) tla_alwaysif( REG_A_ACCESS() ) tla_then ( ( REG_B_ACCESS() ) tla_without ( REG_A_ACCESS() ) )

Assertion Reuse Reuse Assertions for Higher Abstraction Model to Lower Level Convert Callback to Event base (PV -> PVT) Construct Adaptor to extract events from signals (PVT -> CA) NSCa’s Cycle Accurate temporal sequence can be used to construct adoptor for Cycle Accurate Model PV ModelPVT ModelCycle Accurate Model event notifycallback Adaptor Cycle Accurate Assertion Bus Protocol Check Performance Check PVT Assertion Application Protocol Check PV Assertion

Conclusion and Future Work NSCa provides Temporal Assertion Mechanism for Various Abstract Levels Native in SystemC (C++) Some ideas for PVT and PV assertions Future Work More sturdy is needed to refine TLA temporal Primitives Standarization of Callback mechanism is necessary AOP like mechanism for adding callbacks?