Some examples Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Lecture 7.3

2 7.3 Goal  This lecture guides the students through the solution of some simple examples of manual synthesis of sequential networks.

3 7.3 Prerequisites  Lectures 7.1 and 7.2

4 7.3 Homework  Students are recommended to try to solve the exercise by themselves, before looking at the proposed solutions.

5 7.3 Further readings  No particular suggestion

6 7.3 Outline  Example #7.3.1: rising edge detector  Example #7.3.2: palindrome string detector  Example #7.3.3: BCD big endian  Example #7.3.4: BCD little endian  Example #7.3.5: parity checker  Example #7.3.6: Ford Thunderbird light controller  Example #7.3.7: code checker  Example #7.3.8: sequence checker

7 7.3 Example #7.3.1: rising edge detector A circuit is to be designed, having:  An input X  A clock signal CLK, which acts as a proper sampling signal of X, i.e., the frequency of CLK is such that it never happens that two transitions of X occur within a same CLK cycle  An output U, asserted for a clock cycle whenever a rising edge on the input X is detected.

8 7.3 CLK X Waveforms

9 7.3 CLK X Z Waveforms

STG reset H0,0

STG reset 1 H0,0

STG L,0 reset 1 0 H0,0

STG L,0 reset H0,0

STG L,0 H1,1 reset H0,0

STG L,0 H1,1 reset H0,0 0

STG L,0 H1,1 reset H0,0 0 1

State encoding stateencoding H000 L11 H110

STT L,0 H1,1 reset H0,0 0 1 stateencoding H000 L11 H110

STT L,0 H1,1 reset H0,0 0 1 stateencoding H000 L11 H H0  L  H1  y[1:0] x Y[1:0] Z

STT 01 H0  L  H1  y[1:0] x Y[1:0] Z Y[1] = x’ + y[0] Y[0] = x’ Z = y[1]y[0]’

D D x Z D[1] = x’ + y[0] D[0] = x’ Z = y[1]y[0]’ Solution D[0] y[1] y[0] D[1]

Outline  Example #7.3.1: rising edge detector  Example #7.3.2: palindrome string detector  Example #7.3.3: BCD big endian  Example #7.3.4: BCD little endian  Example #7.3.5: parity checker  Example #7.3.6: Ford Thunderbird light controller  Example #7.3.7: code checker  Example #7.3.8: sequence checker

Example #7.3.2: palindrome string detector On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string.

Example #7.3.2: palindrome string detector On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. A circuit to be connected to the serial line is to be designed. It has an output U which is asserted whenever the last 4 values got in input forms a palindrome string. Examples: ANNA – 3993 – 0110

reset

reset

reset

reset

U=0 U=1 reset

U=0 U=1 reset

Outline  Example #7.3.1: rising edge detector  Example #7.3.2: palindrome string detector  Example #7.3.3: BCD big endian  Example #7.3.4: BCD little endian  Example #7.3.5: parity checker  Example #7.3.6: Ford Thunderbird light controller  Example #7.3.7: code checker  Example #7.3.8: sequence checker

Example #7.3.3: BCD big endian On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit groups of 4 bits: each group corresponding to a BCD digit, transmitted MSB first (big endian) A circuit to be connected to the serial line is to be designed. It has an output U which is asserted, for 1 clock cycle, in correspondence of the 4 th bit of each group, if the group itself is a correct BCD digit. BCD

Solution When dealing with circuits that must consider groups of bits, it may be convenient to start from a set of states, one for each possible combination of the PO values. BCD

Solution A,0E,1 reset BCD

Solution A,0E,1 B,0 reset BCD

Solution A,0E,1 B,0 reset C,0 - - BCD

Solution A,0E,1 B,0 reset C,0 D, BCD

Solution A,0E,1 B,0 F,0 reset C,0 D, BCD

Solution A,0E,1 B,0 F,0 reset C,0 D,0 - - H,0 1 - BCD

Solution A,0E,1 B,0 F,0 reset C,0 D,0 I,0 - - H, BCD

Solution A,0E,1 B,0 F,0 reset C,0G,0 0 D,0 I,0 - - H, BCD

Outline  Example #7.3.1: rising edge detector  Example #7.3.2: palindrome string detector  Example #7.3.3: BCD big endian  Example #7.3.4: BCD little endian  Example #7.3.5: parity checker  Example #7.3.6: Ford Thunderbird light controller  Example #7.3.7: code checker  Example #7.3.8: sequence checker

Example #7.3.4: BCD little endian Similar to the previous exercise, with the only difference that BCD digits are transmitted LSB first. BCD

Valid Sequences 00000Y 00018Y 00104Y N 01002Y N 01106Y N 10001Y 10019Y 10105Y N 11003Y N 11107Y N BCD

A,0E,1 B,0 reset  C,0 F,0 D,0 G,0  1   E 0 1 EA BCD

Outline  Example #7.3.1: rising edge detector  Example #7.3.2: palindrome string detector  Example #7.3.3: BCD big endian  Example #7.3.4: BCD little endian  Example #7.3.5: parity checker  Example #7.3.6: Ford Thunderbird light controller  Example #7.3.7: code checker  Example #7.3.8: sequence checker

Example #7.3.5: parity checker On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit strings of 4 bits A circuit to be connected to the serial line is to be designed. It has an output Z which is asserted, for 1 clock cycle, in correspondence of the 4 th bit of each string, if the string itself contains an odd # of 1’s. P4P4P4P4

Example X Z 0X Z 0 P4P4P4P4

B,-C,- reset evenodd P4P4P4P4

B,-C,- D,-E, reset evenodd P4P4P4P4

B,-C,- D,-E,- F,-G, reset evenodd P4P4P4P4

B,-C,- D,-E,- F,-G,- H,0I, reset evenodd P4P4P4P4

reset B,-C,- D,-E,- F,-G,- H,0I, evenodd P4P4P4P4

Outline  Example #7.3.1: rising edge detector  Example #7.3.2: palindrome string detector  Example #7.3.3: BCD big endian  Example #7.3.4: BCD little endian  Example #7.3.5: parity checker  Example #7.3.6: Ford Thunderbird light controller  Example #7.3.7: code checker  Example #7.3.8: sequence checker

Example #7.3.6: Ford Thunderbird light controller A circuit is to be designed to control the back lights of the Ford Thunderbird of The car has,on its back, 6 lights, turned on with different strategies to signal different operations:  Turn left  Turn right  Break  Emergency

t Turn to the right

t Turn to the right

t Turn to the right

t Turn to the right

t Turn to the right

Turn to the left t

t Brake Brake on Brake off

t Emergency

The circuit has:  4 inputs:  LEFT & RIGHT asserted when turning left or right, respectively  HAZ asserted to signal an emergency  BRAKE asserted when the driver is braking  6 outputs, one for each light: Top level LCLBLARARBRC

Input signals are assigned the following priority:  BRAKE has the highest priority  LEFT & RIGHT have the lowest priority  HAZ has an intermediate priority Input priorities

Solution To simplify the design, the BRAKE input can be implemented as follows, and thus not considered any longer in the sequel of the design: FSM BRAKE

IDLE 000 LEFT, RIGHT, HAZ STG

IDLE LCLBLARARBRC 000 LEFT, RIGHT, HAZ STG

 1 IDLELR3 LCLBLARARBRC LEFT, RIGHT, HAZ

 IDLELR3 LCLBLARARBRC LEFT, RIGHT, HAZ

IDLE L1 LR3 LCLBLARARBRC 100 LEFT, RIGHT, HAZ

IDLE L2 L1 LR3 LCLBLARARBRC  0 LEFT, RIGHT, HAZ

L3 IDLE L2 L1 LR3 LCLBLARARBRC  0 LEFT, RIGHT, HAZ

L3 IDLE L2 L1 LR3 LCLBLARARBRC  LEFT, RIGHT, HAZ

L3 IDLE L2 L1 R1 LR3 LCLBLARARBRC 010 LEFT, RIGHT, HAZ

L3 IDLE L2 L1 R2 R1 LR3 LCLBLARARBRC  0 LEFT, RIGHT, HAZ

L3 IDLE L2 L1 R3 R2 R1 LR3 LCLBLARARBRC  0 LEFT, RIGHT, HAZ

L3 IDLE L2 L1 R3 R2 R1 LR3 LCLBLARARBRC  LEFT, RIGHT, HAZ

L3 IDLE L2 L1 R3 R2 R1 LR3 LCLBLARARBRC  1 LEFT, RIGHT, HAZ

L3 IDLE L2 L1 R3 R2 R1 LR3 LCLBLARARBRC  1 LEFT, RIGHT, HAZ

Outline  Example #7.3.1: rising edge detector  Example #7.3.2: palindrome string detector  Example #7.3.3: BCD big endian  Example #7.3.4: BCD little endian  Example #7.3.5: parity checker  Example #7.3.6: Ford Thunderbird light controller  Example #7.3.7: code checker  Example #7.3.8: sequence checker

Example #7.3.7: code checker On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit groups of 5 bits. In each group, the first 3 bits are a data and the remaining 2 bits are a code associated to the data to detect transmission errors. In particular, for each group of bits, the code encodes the number of bits equal to ‘1’ in the data of the same group. Codes are transmitted Most Significant Bit (MSB) first. 3|2

Example #7.3.7: code checker (cont’d) A circuit to be connected to the serial line is to be designed, such that its output OK is asserted for one clock cycle iff, at the completion of a group, no transmission error has been detected. 3|2

STG ko,0 reset ok, |2

STG ko,0 reset ok,1 0 #0,0 0 #1, |2

STG ko,0 reset ok,1 0 #0,0 0 0 #1, #2, |2

STG ko,0 reset ok,1 0 #0,0 #1,0 0 0 #0,0 #1, #2,0 #3, |2 data

STG ko,0 reset ok,1 0 #0,0 #1,0 0 0 #0,0 #1, #2,0 #3, A,0B,0C, okkookko code 3|2

Outline  Example #7.3.1: rising edge detector  Example #7.3.2: palindrome string detector  Example #7.3.3: BCD big endian  Example #7.3.4: BCD little endian  Example #7.3.5: parity checker  Example #7.3.6: Ford Thunderbird light controller  Example #7.3.7: code checker  Example #7.3.8: sequence checker

Example #7.3.8: sequence checker On a serial transmission line X, bits are transmitted synchronously w.r.t. a clock signal CLK, one bit per clock cycle. The line is used to transmit sequences of 1’s and sequences of 0’s. In particular, sequences may have any length, but all the sequences of 1’s must contain an odd # of 1’s, whereas all the sequences of 0’s must contain an even # of 0’s. A circuit to be connected to the serial line is to be designed, such that its output OK is asserted for one clock cycle whenever a transmission errors has been detected. odd even

Solution hint  Since the # of possible states is limited,  list the whole set of states first  fill up the transitions later  erase the unreachable states (if any) odd even

STG #0 even, 0 reset #0 odd, 0#0 odd, 1 #1 even, 0#1 odd, 0#1 odd, 1 #0 even, 1 #1 even, 1 odd even

STG #0 even, 0 reset #0 odd, 0#0 odd, 1 #1 even, 0#1 odd, 0#1 odd, #0 even, 1 #1 even, 1 odd even

STG #0 even, 0 reset #0 odd, 0#0 odd, 1 #1 even, 0#1 odd, 0#1 odd, #0 even, 1 #1 even, 1 Unreachable states: they can be deleted odd even

STG #0 even, 0 reset #0 odd, 0#0 odd, 1 #1 even, 0#1 odd, 0#1 odd, odd even