Universal Verification Methodology (UVM) Benefits Mustafa Khairallah Boost Valley Boost Valley Consulting 1

Outline  Verification Needs  UVM Benefits  Example: I 2 S  Conclusion Boost Valley Consulting 2

Verification Needs Boost Valley Consulting 3 Code Reuse Test Cases & Scenarios Modification Functional Coverage Calculation Generating & Managing Reports Debugging Communication

Verification Needs - Development Boost Valley Consulting 4 Code Reuse Test Cases & Scenarios Modification Functional Coverage Calculation Generating & Managing Reports Debugging Communication

Verification Needs - Compilation Boost Valley Consulting 5 Code Reuse Test Cases & Scenarios Modification Functional Coverage Calculation Generating & Managing Reports Debugging Communication

Verification Needs - Runtime Boost Valley Consulting 6 Code Reuse Test Cases & Scenarios Modification Functional Coverage Calculation Generating & Managing Reports Debugging Communication

Verification Needs - Debugging Boost Valley Consulting Code Reuse Test Cases & Scenarios Modification Functional Coverage Calculation Generating & Managing Reports Debugging Communication 7

Verification Methodologies  Do the same things the same way:  Ease of communication.  Test/Test-bench separation:  Compile once, run many times.  Utilities:  Functional coverage – reporting mechanisms - … etc. Boost Valley Consulting 8

UVM Benefits Boost Valley Consulting 9

UVM Adoption Boost Valley Consulting 10

Test/Test-bench separation Test Writer: Selects sequences, Configures the environment(s) Runs test. Test Environment Bus Agent Active Agent Passive Agent Analysis Agent Register Model Environment Configurations DUT UVC User: Integrates UVCs into environment to test different designs. Env (Test- bench) Developer: UVC Design Complication phase. UVCs Boost Valley Consulting 11

Test/Test-bench separation Test Environment Bus Agent Active Agent Passive Agent Analysis Agent Register Model Environment Configurations Boost Valley Consulting 12 Test Writer: Selects sequences, Configures the environment(s) Runs test. Test UVC User: Integrates UVCs into environment to test different designs. Env (Test- bench) Developer: UVC Design Complication phase. UVCs

Test/Test-bench separation Test Environment Bus Agent Active Agent Passive Agent Analysis Agent Register Model Environment Configurations Boost Valley Consulting 13

Configurability  Controlled by the test writer.  Configurations can be:  Structural configurations.  Runtime configurations.  Provides topological flexibility:  Components can be overridden, removed or configured. Boost Valley Consulting 14

Block 2’ TLM 2.0  UVM is compatible with the TLM 2.0 standard.  Uses port/export communication.  Hides communication details (pin level activities)  Eases customization using configurations & overrides. Block 1Block 2 Boost Valley Consulting 15

Constrained Randomization Boost Valley Consulting 16

Coverage Collector Boost Valley Consulting 17

Checker (Reference Model) Boost Valley Consulting 18

Checker (Assertions) Boost Valley Consulting 19

Built-in reporting mechanisms. Boost Valley Consulting 20

Built-in reporting mechanisms. Boost Valley Consulting 21

Practical Example :I 2 S Boost Valley Consulting 22

Introduction  I 2 S stands for Inter-IC Sound,  DUT is a slave I 2 S transceiver.  It is around 2000 gates.  I 2 S Bus Purpose:  Communicate PCM audio data between integrated circuits.  Characteristics  Separates clock and serial data signals.  Lower Jitter.  Can recover clock from data stream. Boost Valley Consulting 23

UVM Test-Bench Architecture Boost Valley Consulting 24

Limitations in VHDL  No support for test/test-bench separation.  No test termination mechanism.  No randomization algorithm. Boost Valley Consulting 25

Runtime Comparison > 10 Times Reduction!! Boost Valley Consulting 26 Time in minutes VHDL UVM

Summary Conventional Test-benchUVM Test-Bench Mainly simulation-based Limited assertion-based capabilities Simulation based Advanced assertion-based in System Verilog & UVM Mostly directed testing Constrained random testing & directed testing Boost Valley Consulting 27

Summary Conventional Test-benchUVM Test-Bench Can’t automatically guarantee full functional coverage Supports functional coverage Boost Valley Consulting 28

Summary Conventional Test-benchUVM Test-Bench Strongly coupled with DUTLoosely coupled with DUT Requires longer development time Reusability reduces development time Boost Valley Consulting 29

Thank You Questions? Boost Valley Consulting 30