Radiation Effects Challenges in 90nm Commercial-Density SRAMs: A Comprehensive SEE and TID Study Jeff Draper, Y. Boulghassoul, M. Bajura, R. Naseer, J. Sondeen and S. Stansberry University of Southern California Information Sciences Institute This work was supported by the Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office under award No. N Any opinions, findings, and conclusions or recommendations expressed in this presentation are those of the authors and do not necessarily reflect the views of DARPA/MTO or the U.S. Government 1 st Workshop on Fault-Tolerant Spaceborne Computing Employing New Technologies CSRI, Sandia National Labs, Albuquerque, NM May 28-30, 2008

2 Motivations RHBD approach shown to be effective for 90nm designs, within acceptable “1 process generation” penalty Use of RHBD for SRAMs poses bigger challenges SRAM density achieved through aggressive design rule waivers Cell-level radiation hardening using typical RHBD techniques compounds area/speed/power penalties Traditional circuit-based RHBD approach Hardens control structures and individual memory cells SRAM BER largely determined by the raw BER of the memory cell Objective: Investigate best rad-hard SRAM performance achievable through hybrid hardening approach Harden control structures but leave commercial SRAM cell density and technological scaling of individual memory cells intact Mitigate SEUs (SBU/MBU) with device-centric ECCs Leverage intrinsic process hardness for improved reliability

3 Outline SRAM test chips overview SEU response Heavy-Ions Protons Latchup response TID and temperature annealing 24C, 100C and 150C Summary and conclusions

4 Overview SRAM Test Chips Fabricated 4 SRAMs in 9LP and 9SF processes (1 baseline, 1 hardened in each) Key design objectives: Use commercial core memory cells (FP118 and E123) Harden peripheral circuitry using TMR, annular gates, interleaving

5 RHBD SRAM Approach/Design Block SET Hardening Annular gates (TID) Decoders, ECC, Timing #1Decoders, ECC, Timing #2 Decoders, ECC, Timing #3 Voter TMR Bit Interleaving (MBU Mitigation) Guard rings (SEL) Cell TID & SEL Hardening Array SEU Hardening (SEC/DED)

6 - Single Event Effects - SEU

7 SEU Raw Cross Sections HI Test Results BASELINE HARDENED Data collected at LBNL 88” Cyclotron, 10 MeV cocktail, core voltage 10% below nominal, 100 MHz tester. Fluence range 1e7-1e5. #Errors>256 ea. pt. LP SF LPSF Memory Patterns={00,11,10}, Static/Dynamic = {s, d}; LP Dynamic Access Rate 2.2 KHz per bit; SF Dynamic Access Rate 718 Hz

8 SEU Cross Section Calculations Pre-ECC and Scrubbing Device Configuration Weibull Cross-Section Parameters (per bit) Raw Upsets / Bit-Day Before ECC and Scrubbing Geo. Orbit Eq. Orbit 3,000 km (Rad. Belts) Max GCRMin GCR Solar Flares Worst Week aX0ws sfb3.3e e-77.2e-81.4e-42.4e-4 sfh3.3e e-76.2e-88.6e-51.1e-4 lpb1.8e e-73.8e-82.4e-52.0e-6 lph1.8e e-73.3e-83.7e-53.8e-5 Calculations using CREME96, 100 mil shielding. AP8 model for equatorial orbit. Weibull(x) = [ a ]*[ 1-e { ((x-x0)/w)) } ] SF cross-section ~ 2-3 X higher than LP, likely due to lower Vdd No cross-section dependence on static vs. dynamic testing Minor differences between baseline and hardened suggest little impact of TMR control circuitry s

9 *. Figures assuming 22-bit code from “Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100nm SRAMs”, IEEE TNS Vol. 54, pp , Aug SEU Model ECC and Scrubbing * 1.P(error) depends on the ratio of the device’s memory array SCRUB RATE and its RAW BER, and ECC applied 2.Overall reduction in error-rate is relative to starting physical raw BER.  Example: Scrub rate=10 0, Physical BER=10 -6, Single-bit ECC, improves BER by – New Effective BER Goal: Assume once/10 seconds scrub rate and BER; the device can tolerate up to errors/bit-day with single-bit ECC, errors/bit-day with double-bit ECC. Constant 1E-10 BER curves vs. ECC and Scrub Rate BER reduction vs. ECC and Scrub Rate P(error) per scrub vs. ECC and Scrub Rate 1 3 2

10 Comparison of ECC Model with SEU Experimental Data LPH STATICSFH STATICLPH DYNAMICSFH DYNAMIC Scrub Rate /bit1 / Run2.22 kHz0.718 kHz Raw BERErrors / Run / Memory Size Errors / Run / Time (Secs) / Memory Size Effective BEREquation AEquation BEquation AEquation B Total SBUS (All SEU Runs)13,00412,1179,901*9,372 Total Bit Errors Observed (Not Corrected by ECC) 7,305195NO ERRORS Total Bit Errors Predicted by the Model for a Given Scrub Rate, Raw BER and ECC 7, (< 1 word) Approximate Effective BER Equations for Single-bit- correcting 22-bit word and Double-bit-correcting 15-bit word Raw BER 1 + Scrub Rate/Raw BER 300 Equation A ~ Raw BER 1 + Scrub Rate/Raw BER 15 2 Equation B ~ (1-bitt ECC)(2-bitt ECC) Distribution of observed errors from measurements matches the ECC model very well Proper error correction code (ECC) and modest scrubbing rate combination ensures a BER better than errors/bit-day in all orbital scenarios

11 SBU and MBU analysis vs. Effective LET Single and Multi Bit Upset Distributions vs. Effective LET for LP and SF SRAMs 9LP 9SF Large differences in the SBU/MBU distribution between LP and SF SRAMs for similar LET values Particularly noticeable for LET> ~10 (MeV-cm 2 /mg) Saturating cross-sections have LET-dependent error distributions LET of 31 and 117 have comparable cross-sections but different distributions

12 SEU Proton Testing SRAM typeBit configurationsAverage cross-section/bit.cm 2 9LP BaselineAll 0, All 1, E-14 9LP HardenedAll 0, All 1, E-14 9SF BaselineAll 0, All 15.92E-14 9SF HardenedAll 0, All 17.24E-14 Saturating cross-section of 9SF and 9LP SRAMs for a 200MeV proton exposure. IBM 90nm commercial density SRAM cells have a very low upset threshold From 3D TCAD simulations, worst-case Q crit ~1.1fC With an SRAM cell threshold LET < 0.5 MeV.cm 2 /mg, protons could potentially become capable of inducing SEUs through direct ionization Possible drastic increase in raw memory cell BER Could flood 1bit and possibly even 2 bit ECC schemes SRAM saturating cross-section still well behaved for worst-case 200Mev proton exposure (~ errors/bit.cm 2 ) Proton upsets from nuclear interactions, no direct ionization 90nm Data collected at Indiana University cyclotron facility, 200Mev line. Proton flux ~ particles/cm 2. s. Max TID for each tested part ~ 20Krad.

13 - Single Event Effects - Latchup

14 Latchup in 90nm SRAMs Experimental Condition Device LP BASELINELP HARDENEDSF BASELINESF HARDENED High V High Heat (worst case) Vcore = 110%1.32 V1.1 V Temp = High125 C LET ThresholdBetween 0.87 and 2.22> 117 High V No Heat Vcore = 110%1.32 V Not applicable Temp = Room~ 24 C LET Threshold> 117 Latch Up Onset and Release Voltages VcoreBetween V Temp = High125 C LET> 117 SF appears to be SEL immune LP appears to be SEL immune if, and only if: –At room temperature over voltages up to 110% Vcore, OR –At lowered voltage over temperatures up to 125 C All SELs observed in LP were non-destructive LP latchup appeared as a single step-function of ~50 mA Data collected at LBNL 88” Cyclotron, 10MeV cocktail. High T applied through RTD strapped to PGA package and PID control

- Total ionizing Dose -

16 9LP/9SF TID and Room T 0 Annealing Responses All devices 200 rads/sec, Max Temp < 30 C, removed ~15 minutes for measurement LP irradiated under 10 pattern & measured under 01; SF irradiated under 00 pattern & measured under 11 TID-induced Core leakage currents of Baseline and Hardened SRAMs were identical for a given process TID response of SRAM Core is dominated by memory array leakage 9LP SRAM: - ~ 1000X increase in Core leakage 2Mrad - 4/4 devices functional failure [1000 <X<1300] krads - 4/4 devices fully functional after 7 days annealing - Leakage ~ 30X after 140 days 9SF SRAM: - ~ 50X increase in Core Leakage 2Mrad - 20X pre-rad leakage but same level as 2Mrad - 4/4 devices functional failure [600<X<1000] krads - 2/4 devices fully functional after 7 days annealing - Leakage ~ 8X after 140 days 9LP and 9SF SRAM Core leakage currents dynamics as a function of TID and 24C anneal

17 9LP/9SF TID and Room T 0 Annealing Responses (cont.) All devices 200 rads/sec, Max Temp < 30 C, removed ~15 minutes for measurement LP irradiated under 10 pattern & measured under 01; SF irradiated under 00 pattern & measured under 11 TID-induced IO leakage currents showed drastic differences between hardened and unhardened IO pads Hardened pads should be used whenever possible Major impact on reliability at negligible performance penalties 9LP SRAM: - Hardened IO pads (MRC design) - ~ 1  A IO leakage up to 2Mrad 9SF SRAM: - Unhardened IO pads (Artisan cells) - ~ 10 4 X increase in IO 2Mrad - Leakage ~ 2000X after 140 days 9LP and 9SF SRAM IO leakage currents dynamics as a function of TID and 24C anneal

18 9LP/9SF TID Responses for 100C and 150C anneals All 9LP and 9SF SRAMs respond very well to a temperature annealing For 100C, Core leakage currents are within 3X of pre-rad < 100 hours For 150C, pre-rad Core leakage levels are reached within 5 hours 9LP and 9SF SRAM Core leakage current variation as a function of annealing temperature The unhardened IO did not respond well 100C anneal is ineffective: still ~ 1000X above pre-rad after 200 hours 150C anneal is slightly better with 10X above pre-rad after 60 hours

19 TID Radiation Hysteresis All SRAMs re-exposed a second time NEVER exhibited functional failure up to 2Mrad Successive TID exposure and annealing cycles induced a shift in the SRAM leakage characteristics: Lateral shift: the SRAM start degrading sooner than in its first irradiation Vertical shift: the current “saturation” level is lowered But the true mystery improvement to the SRAM reliability is…

20 Single Event Upsets (SEU) and Bit-Error-Rate (BER) –Proper ECC strength, bit interleaving and modest scrubbing rate combination ensures an SRAM BER better than errors/bit-day in all space environments investigated. Single Event Latch-up (SEL) –9SF commercial memory cells are latch-up immune. –9LP commercial memory cells are latch-up free only under high temperature or high voltage, but not both. –Voltage scaling is likely to mitigate SEL concerns for core voltages < 1.1V. Total Ionizing Dose (TID) –90nm SRAMs showed to be intrinsically resilient up to 300krad, but a substantial static leakage increase happens past 500krad (10X). –TID Hardened IO pads should be used whenever possible. –9LP/9SF SRAMs are very responsive to temperature treatments: All SRAMs regained pre-rad nominal currents within 5 hours of 150°C annealing after 2Mrad TID exposure. All ICs recovered from catastrophic loss of functionality. –Successive exposure and annealing cycles induced hysteresis in the SRAM leakage characteristics: The current degradation starts earlier However, the maximum leakage at 2Mrad is lower than for the first irradiation. –All ICs that underwent complete thermal anneal NEVER exhibited functional failure up to 2Mrad when re-exposed. Summary and Conclusions