Activity-Sensitive Architectural Power Analysis for the Control Path Paper by Landman and Rabaey University of Massachusetts, Amherst ECE697M Low Power Architecture (Fall’03) Professor Csaba Andras Moritz Presentation by Nathir Rawashdeh

Outline Motivation Control Path Power Modeling (ABC method) A Power/Area Analyzer (SPA) Results Conclusions

Motivation Power consumption is a critical design criterion Transistor-level tools such as SPICE and PowerMill are accurate but cannot be applied early in the design process where changes are cheaper. Most high-level tools (for control path modeling) model complexity only and can be off by >2x In this paper: a high-level model for control path that includes effects of activity.

Control Path Power Modeling (ABC method) Controllers: Direct the sequence of ops to be executed by the data- path Initiate Mem accesses and data transfers Activity-Based Controlle (ABC) model uses a FSM to model controllers. Finial implementation power estimate a function of: Target style State machine description Npi : # primary input bits Npo : # primary output bits Ns : # state bits

Control Path Power Modeling (ABC method) Example of a controller (ROM) Cs are extracted through a library characterization process where Caps are measured for different input-output activities. Ni : # inputs No : # outputs Cap model =>

Control Path Power Modeling (ABC method) IRSIM-CAP is a switch-level simulator to which the results from the ABC model are compared. For different complexities (No), C increases as the probability output signal goes from 0 to 1. => activity matters ABC model error: Avg 2.5 % Max 4.5 % Similar results for PLA instead of ROM. PLA Has less complex decoding at the input

Control Path Power Modeling (ABC method) Random logic (i.e. standard cell) controllers much less regular than ROM or PLA => harder to model Caps Agreement not as good as ROM or PLA, but rms error is acceptable at 15.1 %

A Power/Area Analyzer (SPA) SPA is an architectural Power/Area analyzer. In this paper, the ABC model for data-path power has been incorporated into SPA. In the following slides, SPA modeling performance has been measured against actual layouts and switch-level simulation (using IRSIM-CAP)

Results ->Divider Example Divider: Data-path intensive. Newton-Ralph divider at 1.5V and 5 MHz SPA’s error: Area within 6% of actual. Power: 2% to 27%; avg 6% Modeling with SPA is 24x quicker than with IRSIM-CAP => Very good at early design stage

Results ->Speech Recognition Ex. Speech Recognition FSM example: control intensive 100 staes, 3.3 MHz, 1.5V SPA error: Area avg 17.3%, max 22% Power avg 12.6%, max 29% Std Cell difficult to model SPA much quicker tool than layout or switch-level

Results ->Microprocessor Ex. Microprocessor example: Memory Intensive Program: Multiplier Fibonacci seg. Generator Circular queue 10 MHz, 1.5V, 16bit proc. SPA error: Power –4%, -.9%, -2.4% Area within 8% SPA is quicker tool

Conclusions Paper introduced the ABC model for control path power analysis on the architecture level. ABC model accounts for effects of activity and complexity on power consumption. ABC model incorporated into SPA power/area analyzer. SPA now analyzes control path + data path, memories and interconnect areas Comparing SPA results with switch-level layout simulations: - SPA error rate: average 7% - ABC error rate: average 13%, max 29% - Area est. error: average 14% Activity-sensitive power modeling: fast, accurate and useful in early design stages.