LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa1 CMS Upgrade for Super-LHC Fabrizio Palla INFN Pisa

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa2 Outline CMS activities for SLHC Upgrades needed to withstand a factor 10 higher luminosity Machine related questions from the Working Group 1 Bunch spacing Experimental beam pipe Space requirements Maintenance Installation and commissioning

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa3 SLHC & CMS CMS has held three workshops on SLHC Feb General startup July Mostly Tracker, Trigger and Electronics July Trigger upgrades Important starting point Most CMS systems will survive and continue to operate without changes to inaccessible electronic systems Implies some constraints on future machine operation Major exceptions Tracker - which is expected to be entirely replaced for SLHC Trigger - rebuild L1 processors + there is a strong belief that Tracker information is necessary for L1 trigger

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa4 Radiation Issues Assumed integrated luminosity LHC: 500 fb-1 SLHC 2500 fb-1 Main consequences Tracking detectors will suffer the largest damage Need to be rebuild entirely ECAL Endcaps need shielding HCAL HCAL Endcaps too much radiation, need reconsider the technology Muons YE4 better shielding ME1 needs shielding

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa5 Radiation Issues SLHC Radiation tolerance of current pixel system can be pushed to 3x10 15 cm -2

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa6 Tracker Upgrade Higher granularity and more pixels are required Power requires major effort & new ideas Chip voltages reduce with technology evolution, currents may (??), but number of channels will not Need to bring increased total currents through volumes which can’t expand Material budget should not increase Large systems are hard to build Qualification must be taken seriously True industrial production is likely to be required Sensors are one of many issues Any new material technology must be large-scale commercial within ~5 years Electronic technology evolution will bring benefits and also more complexity and much difficult work

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa7 First ideas for a New Tracker Proposed 3 Pixel Systems that are adapted to fluence/rate and cost levels Pixel #1 max. fluence system ~400 SFr/cm 2 Pixel #2 large pixel system ~100 SFr/cm 2 Pixel #3 large area system Macro-pixel ~40 SFr/cm 2 8 Layer pixel system can eventually deal with 1200 tracks per unit pseudo – rapidity

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa8 Intermediate prototype Installation of modest prototype system at t p = t 0 + 5y Less cost and lower risk Less substantial case for support needed More chance of resources, on short time scale Allows trial of components or devices, which may still evolve Human time-scale Prototype contained in the volume from pixel layer 0 to 4 Need to use/reuse service space for pixels Will allow the study of New technologies Occupancy/rates Beam backgrounds Trigger Data links

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa9 ECAL Endcaps Repair of Supercrystal array would require the dismounting of readout electronics on rear of backplate High activation levels, access time limited Supercrystals and their internal components are inaccessible and cannot be replaced. 5mSv/h Unshielded dose rate* 0.2mSv/h  =3  =1.48 *3300 fb -1

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa10 HCAL Endcaps Scintillator under radiation form color centers that reduces the collected light yield. Current operational limit ~ 5 Mrad Should change the technology in the HCAL endcaps Dose per year at SLHC ECAL HCAL

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa11 Muon chambers Need better shielding of YE/4 (likely to be done before SLHC proper) Need better shielding for ME/1

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa12 Trigger at SLHC Occupancy Degraded performance of algorithms Larger event size to be read out New Tracker: higher channel count & occupancy  large factor Reduces the max level-1 rate for fixed bandwidth readout. Trigger Rates Try to hold max L1 rate at 100 kHz by increasing readout bandwidth Avoid rebuilding front end electronics/readouts where possible Rebuild L1 processors to work at 80 MHz Already few cases use 160 MHz processing Use 40 MHz sampled data to produce trigger primitives with 12.5 ns resolution Radiation damage -- Increases for part of level-1 trigger located on detector

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa13 Tracker Trigger at L1 Muon L1 Trigger rate at L = cm -2 s -1 Note limited rejection power (slope) without tracker information Must develop Tracker Trigger at L1 Export some HLT algorithms to L1? Lot of activities going on

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa14 DAQ System LHC DAQ design: A network with Terabit/s aggregate bandwidth is achieved by two stages of switches and a layer of intermediate data concentrators used to optimize the EVB traffic load. RU-BU Event buffers ~100GByte memory cover a real-time interval of seconds SLHC DAQ design: A multi-Terabit/s network congestion free and scalable (as expected from communication industry). In addition to the Level-1 Accept, the Trigger has to transmit to the FEDs additional information such as the event type and the event destination address that is the processing system (CPU, Cluster, TIER..) where the event has to be built and analyzed. The event fragment delivery and therefore the event building will be warranted by the network protocols and (commercial) network internal resources (buffers, multi-path, network processors, etc.) Real time buffers of Pbytes temporary storage disks will cover a real-time interval of days, allowing to the event selection tasks a better exploitation of the available distributed processing power.

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa15 Beam pipe CMS does not expect any change in the beam pipe material Beryllium beam pipe at the IP Beam pipe diameter set by the dynamic aperture of the reproducibility of the beam Current diameter at the IP is 58 mm Q: how much can be reduced to allow tests of new structures close to the beam for normal LHC running? Forward beam pipe diameter can go to 400 mm after HF and its shadow

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa16 Forward shielding rotating system is near the limits of mechanical strength new concept or supplementary system needed

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa17 Forward region:shielding upgrade pots for 2’nd set of jacks at each end built into UXC floor. would form basis of support for a supplementary structure closing around the existing RS time needed to open and close CMS would increase significantly (~1 week per shutdown)

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa18 Bunch spacing The consequences of switching away from 12.5 ns to 10 or 15 ns could be severe for CMS. If we can stay with 12.5 ns we may not have to rebuild much of our ECAL, HCAL and Muon front end electronics. If we change to 10 ns or 15 ns then we most likely have to rebuild most of this electronics. Need a review within CMS to give exact statements … but guess that the cost could easily exceed 100 MCHF. Q: it will be beneficial for us if we could only have a “default” scenario and a backup one for the parameters of the SLHC Offer solid starting point for R&D for the experiments Allow costs/benefits to be quantified

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa19 Shorter L* Any element of the machine inside CMS will have consequences in the forward detectors and need to be studied and evaluated once having in hand a proposal from the machine group. Can accommodate some elements, but it will depend from the proposal Might re-design the forward shielding Probable increased sensitivity to beam accidents: super BCM needed It would be extremely beneficial the experience gained in running the LHC

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa20 Maintenance The increased activation will seriously affect the maintenance of the detector <10 hours at the Tracker end-flange and 1 hour at the inner ECAL Endcap to reach 5mSv = 1year allowed dose. Those detectors that will not be replaced after the LHC should be very reliable by then Not excluded some systems will be less radiation tolerant than expected. Remote handling might become mandatory in the design of the new detectors and should probably developed for the old ones.

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa21 Installation and commissioning issues Not all changes can be made in a single shutdown. Installing new shielding might be in conflict with some new detectors installation Most likely one or more extended shutdowns (  1 year) will be needed Tracker installation will take 6 months Commissioning of the new detectors will be an additional delay We will get more inputs from the LHC experience Likely to take at least 6 months after the last cable is connected Q: How much time is foreseen for installation of the new machine?

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa22 backup

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa23

Roland HorisbergerCMS SLHC workshop Feb Pix Sys #1 : 3 layers 330 mW/cm 2 High  pix 400 SFr/cm 2 Pix Sys #2 : 2 layers 130 mW/cm 2 Large pix 100 SFr/cm 2 Pix Sys #3 : 3 layers 45 mW/cm 2 Macro pix 40 SFr/cm 2 Eta =1.4  Area = 18.3 m 2 Mechanics etc. not in costs! Strip detector ~25 mW/cm 2 Cost & Power estimate for new Tracker

LHC-LUMI05 31/8-3/ ArcidossoFabrizio Palla INFN Pisa25 Level-1 Latency Present Latency of 3.2  sec becomes 256 crossings Assuming rebuild of tracking & preshower electronics will store this many samples Do we need more? Yield of crossings for processing only increases from ~70 to ~140 It’s the cables! Parts of trigger already using higher frequency How much more? Justification? Combination with tracking logic Increased algorithm complexity Asynchronous links or FPGA-integrated deserialization require more latency Finer result granularity may require more processing time ECAL digital pipeline memory is MHz samples = 6.4  sec Propose this as SLHC Level-1 Latency baseline