Utilizing Printed Electronics Methods for the Fabrication of Multi-layer PC Boards D. R. Hines Laboratory for Physical Sciences College Park, MD John Bolger, Leon Lantz Department of Defense, Ft Meade, MD Rich Lewis and Rick Trudeau KeyW Corporation, Hanover, MD

Goal: Demonstrate the capability of additive manufacturing to fabricate multi-layer PC boards on demand. Utilize a 2-layer power supply design requiring a 1 Amp current carrying capability. Print alternating layers of Silver nano-particle (AgNP) and polyimide (PI) inks. Populate, functionally verify, and perform reliability testing of 14 boards. Overview

Requirements Metal Ink Dielectric Ink layer 2 layer 1 20 mm 16 mm Electrical Current Requirement: 1 Amp Future Layers : Minimum Feature size & pitch <100 um Feature Sizes: Biggest 2 – 5 mm Smallest 250 um

Printing Methods Syringe Ink-Jet Aerosol-Jet

Considerations for Materials Selections Droplet Formation Substrate Wettability Drying/Sintering Temperature Solvent CompatibilityThermal Compatibility

Polyimide coated SiO 2 /Si substrate Ag nanoparticle ink – Solvents: IPA, Ethylene Glycol – Thermal: requires sintering at 255 ˚C to obtain resistivity 6 x Ω m Polyimide ink – Solvent: NMP – Thermal: requires thermal cure up to 300 ˚C Selected materials are stable to all solvent and thermal processing requirements Materials

Ag ink: – Print speed3 mm/sec – Tip Diameter150 um tip – Ink Stream Diameter 40 um – 200 pL/sec (est.) PI ink: – Print speed6 - 8 mm/sec – Tip Diameter300 um tip – Ink Stream Diameter180 um – 7000 pL/sec (est.) Print Parameters

Thermally oxidized Si wafer Spin coated polyimide (5 um) – Cure: 255 ˚C, 90 min First Metal Layer (5 um, 2 Passes) and sinter Dielectric Layer (10 um, 2 Passes) and cure Second Metal Layer (5 um, 2 Passes) and sinter Mount substrate on carrier board Stencil print conductive adhesive Pick-and-place Thermal Cure using reflow oven Removal from Carrier board Mounted on test board Process Flow Board Fabrication Steps Component Assembly Steps

Serpentine Fill Perimeter Fill BorderFill Pitch Pattern Fill Schema Printer Process Issues Aerosol-jet printing requirement for the fabrication of Solid Features

40  m wide line 200  m wide line Polyimide Dielectric layer Ag nanoparticle Ink Sintered at 255 ˚C Printed Test Structures Cartoon of Test Structure

Evaluation of Printed Structures Printed Interconnected Layers Printed two-layer Structure Ag Si PI Si Ag Cross-sectional Measurements

Measured Width,  m Targeted Width,  m Number of Print Passes Evaluation of Printed Structures Width Measurements

Number of Print Passes Measured Thickness,  m Targeted Thickness,  m Targeted Width Evaluation of Printed Structures Thickness Measurements

R =  L (1/A)  = (6.4 ± 0.1)x10 -8  m Resistance,  Measured Area -1,  m -2 Calculated Measured Evaluation of Printed Structures Resistance Measurements

Evolution of 2-layer Board Design 1 st Gen 2 nd Gen 3 rd Gen 1-layer Power Supply Board (Ink-Jet printed)

Bottom LayerTop Layer Required connections ‘vias’ 2-Layer Board Artwork Metal Layers and Interconnects

Creation of Dielectric layer Metal Layers overlap Remove overlap at ‘vias’ 2-Layer Board Artwork

Bottom Metal Layer Top Metal Layer Dielectric Layer Final Artwork 2-layer Power Supply Board

~1 mm Build up of 2-layer Boards (26) 2-layer Power Supply Boards Fabricated and Submitted for Reliability Testing

2-Layer Board Performance Test Process

Eight (8) boards in Temperature Cycling – 2000 cycles from 0 to 90 ˚C Six (6) boards in 90 ˚C – Over 2200 hours to date Six (6) boards to Enter Humidity Testing – 85 ˚C/85% RH Reliability Evaluation

Performance Test Results High Temperature Operational Life Testing at 90 ˚C Total of 18 Individual Voltage Regulators - After more than 2000 hours at 90 ˚C 14 Still Operational 2 Show fluctuations & 2 ‘Dead’

4-Layer Boards - Original Artwork Dielectric 3Dielectric 2Dielectric 1 Metal - Bottom Metal - Sig2 Metal – Sig1Metal – Top

4-Layer Boards - Direct-write Artwork Dielectric 3Dielectric 2Dielectric 1 Metal - Bottom Metal - Sig2 Metal – Sig1Metal – Top

Continue reliability evaluation (2-layer boards) – 85 ˚C/85% RH Fabrication of 4-layer boards Future Work

C =  r  0 (A/d) Material rr C (1  m x 1 mm 2 ) C (1  m x 1 cm 2 ) Polyimide dielectric325 pF1 nF Barium Titanate nanoparticle dielectric pF12 nF Dielectric constants of high-k Materials SiO Al 2 O 3 9 HfSiO 4 11 ZrO 2 25 HfO 2 25 Ta 2 O 5 27 La 2 O 3 30 LaAlO 3 30 Nb 2 O 5 35 TiO 2 30–40 (Anatase), 80–100 (Rutile) BaTiO SrTiO Pb(Zr,Ti)O 3, (Pb,La)(Zr,Ti)O CaCu 3 Ti 4 O M. Osada and T. Sasaki, Adv. Mater. 24, 210 (2012) Printed Capacitors

Integrated Components Si Capacitors as Substrate Capacitor Interconnect layer Power Supply Layers

Hybrid Printed Electronic Device on Kapton 2x4 array of 200 nm Thick Si Semiconductor Elements Transfer Printed onto a Kapton Substrate Next Step: Add dielectric Layer and Gate Electrode. Ag Nanoparticle Ink Source Drain