Custom Implementation of DSP Systems School of Electrical and A 32Gb/s Wireline Receiver with a Low-Frequency Equalizer, CTLE and 2-Tap DFE in 28nm CMOS [1] Custom Implementation of DSP Systems Rasool Faraji S.R.Faraji@ut.ac.ir University of Tehran College of Engineering School of Electrical and Computer Engineering Spring 1392

CONTENT Introduction Receiver Architecture Measurement Results Equalization ISI Channel Characteristics Receiver Architecture Measurement Results Technology and Core Areas and Power Consumption References

Equalization Characteristics Equalization ISI Equalization implementations TX FIR (FFE) RX FIR RX CTLE RX DFE Characteristics Reduce the ISI Reduce the BER Improve the high frequency losses Improve the low frequency losses Fig. 1. Frequency response of the channel and equalizer[5] Fig. 2. Eye Diagrams befor and after Equalization[6]

Channel Characteristics Channel loss at very low frequencies is dominated by the skin effect Rest of the channel loss is mainly due to the material properties i.e. dielectric loss Low-frequency loss has a very gentle slope Conventional equalizers such as CTLE and FFE have a 20dB/dec slope which doesn’t match A new type of equalizer is needed with a gentler equalization slope Fig 3. Channel Loss [10] Fig 4. Channel Response [6]

Receiver Architecture Input-Termination Network 2-Tap Speculative DFE CTLE LFEQ Boundary Sampler Clock Recovery Equalizer Adaptation Phase Interpolator CML to CMOS DDC Fig 5. Receiver block diagram [1]

Receiver Architecture Two-tap Speculative DFE Boundary Sampler Error Sampler Linaer Transconductor Circuit(LTC) Fig 6. Data path with two-tap speculative DFE, boundary and error path [1]

Receiver Architecture CTLE Implementation Improve the high frequency losses Provides large boost (0 to 15dB) at high frequencies CTLE and speculative 2-Tap DFE reduce ISI due to dielectric loss Fig 7. CTLE Implementation [1]

Receiver Architecture Low-Frequency Equalizer (LFEQ) Improve the low frequency losses An equalizer with a closely placed zero and pole approximates the gentler slope Implements a small amount of equalization (0 to 4dB) to compensate for the gentle slope of the low frequency Fig 8. low-frequency equalizer Implementat ion[1]

Measurement Results Improve the Low frequency losses Jitter (DDJ) improved from 0.42UI to 0.21UI with the LFEQ Fig 9. Frequency-domain and time-domain responses of a backplane channel with and without low frequency equalization [1]

Measurement Results BER improved from 10 −7 to < 10 −12 with 37dB loss at 16GHz (40dB total loss with receiver package) Fig 10. Channel Insertion Loss [1] Fig 11. 32Gb/s PRBS31 Bathtub Curve [1]

Fig 12. Receiver′s differential input return loss measurement [1] Measurement Results RX Differential Return Loss better than 10dB from 0 to 20GHz Fig 12. Receiver′s differential input return loss measurement [1]

Technology and Core Areas and Power Consumption 28 nm CMOS Technology 0.9 V supply Area: 1200μm x 275μm Power: 240mW Fig 13. Chip micrographs [1]

References [1] Parikh,S,Kao.T, Hidaka.Y,Jian Jiang, Toda.A, Mcleod.S, Walker.W, Koyanagi.Y, ShibuyaT, Yamada.J,“A 32Gb/s Wireline Receiver with a Low-Frequency Equalizer, CTLE and 2-Tap DFE in 28nm CMOS,” in ISSCC Dig. Tech. Paper.s, pp. 29-28, Feb 2013. [2] J. Bulzacchelli et al., “A 28Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32nm SOI CMOS Technology,” in ISSCC Dig. Tech. Papers, pp. 324-325, Feb 2012. [3] J. Savoj, et al., “A Wide Common-Mode Fully-Adaptive Multi-Standard 12.5Gb/s Backplane Transceiver in 28nm CMOS,” in VLSI Circuits Dig. Tech.Papers, pp.104-105, June 2012. [4] Y. Hidaka, et al., “A 4-Channel 10.3Gb/s Transceiver with Adaptive Phase Equalizer for 4-to-41dB Loss PCB Channel,” in ISSCC Dig. Tech. Papers, pp.346-347, Feb 2011. [5] Y. Hidaka, et al., “A 4-Channel 1.25-10.3Gb/s Backplane Transceiver Macro With 35dB Equalizer and Sign-Based Zero-Forcing Adaptive Control,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp.3547-3559, Dec. 200. [6] Sam Palermo Analog & Mixed-Signal Center Texas A&M University.“ Lecture 7: Equalization Introduction & TX FIR Eq “, ECEN720: High-Speed Links Circuits and Systems Spring 2013.

Thank You