Design of High-Speed Laser Driver Using a Standard CMOS Technology for Optical Data Transmission Dissertation Defense Presentation By Seok Hun Hyun Advisor: Martin A. Brooke November 2004

Outline  Introduction  Background  Design of A High Current Laser Driver  Design of A Low Power Laser Driver  Thin Film Laser Integration onto CMOS circuits  Conclusion and Future Research

Introduction  Objective Design of laser driver for optical data transmission  Using a standard CMOS technology  Studying the behavior of circuit performance with parasitic components  Working at commercially interesting high- speed and low power consumption

Introduction  Fundamental constraints in electronic communication links  Noise, Interference, Power, Cost, etc.  Use of optics as a replacement for electronics  LAN, MAN, board-to-board and chip-to-chip interconnects

Background  Optoelectronic Links

Background  Eye Diagram EYE Noise Margin Logic “1” Logic “0” Jitter Signal Distortion

Background  CMOS technology Low power Low cost High yield Higher degree of integration Vast standard cell library  TSMC 0.18 um mixed-signal CMOS

Background  Laser Driver The electro-optic interface limits the maximum speed of system Simple current switch responses to the input signal modulated with data stream Critical challenge: To deliver large current with very short rise and fall times since the bandwidth is trade off for large current.

Background  Examples of laser driver Reference: Jerry D. Gibson, The Communications Handbook, CRC press, 1996.

High Current Laser Driver  Required to be other types of lasers FP, DFB, MQW, etc.  More than 20 mA modulation currents  A driver for LVDS standards Input: 100 mV p-p Speed : > 10 Gbps Output current: Mod. 0~40 mA, Bias : 0~30 mA

High Current Laser Driver  Hard to design a current switch with LVDS input amplitude (100 mV p-p )  Require pre-driver stages  Bandwidth Enhancement Technique Shunt peaking Source degeneration Cherry-Hooper topology

High Current Laser Driver  Shunt peaking

High Current Laser Driver  Source degeneration

High Current Laser Driver  Cherry-Hooper topology

High Current Laser Driver  Pre-drive stage (a) Active inductor (b) CH topology

High Current Laser Driver  Laser driver with CH topology

High Current Laser Driver  Eye diagram at 10 Gbps

High Current Laser Driver  Laser driver and simulation at 10 Gbps

High Current Laser Driver  Eye diagram at 10 Gbps

High Current Laser Driver  Specifications PerformanceLD with the CH LD with active inductors Speed10 Gbps Input100mV p-p Output Mod: 40mA p-p Bias: 30mA Mod: 40mA p-p Bias: 30mA Power694 mW312 mW

High Current Laser Driver SpeedMod.InputPower Petersen’s work [Ref] 10 Gbps30 m500 m492.2 mW This research10 Gbps40 m100 m312 mW  Comparison [Ref]:A. K. Petersen, K. Kiziloglu, T. Yoon, F. Williams, Jr., and M. R. Sandor, "Front-end CMOS chipset for 10 Gb/s communication," presented at Proceedings of 2002 IEEE Radio Frequency Integrated Circuits Symposium RFIC, 2-4 June 2002, Seattle, WA, USA, 2002.

Low Power CMOS Laser Driver  Parallel Optical Interconnects (POI) are available for rack-to-rack communication at bandwidth of up to 30 Gbps with 12 channels of 2.5 Gbps operation  Next generation POIs will operate at 10 Gbps  The key to demonstrate such links is low power laser driver and receiver

Low Power CMOS Laser Driver  Design Goal  Differential topology Immune to delta I noise SpecificationsGoal Speed Greater than 10 Gbps CurrentBias: > 10 mA Mod.: > 10 mA PowerAs low as possible Current density< 1 mA/um 2

Low Power CMOS Laser Driver  Simulation Process IC technology, Circuit topology Schematic-based simulations  Verification of function of circuits Layout of circuit Parameter extraction from layout Re-simulations with the extracted Check the specifications

Low Power CMOS Laser Driver  Schematics

Low Power CMOS Laser Driver  High speed laser model

Low Power CMOS Laser Driver  Simulation without packaging parasitics  Input : 800 mV p-p PRBS  Speed : 10 Gbps  Mod. : up to 10 mA p-p  Power : 62.5 mW

Low Power CMOS Laser Driver  Simulation with packaging parasitics Wire-bonding parasitics Traces on test board Soldering and cable

Low Power CMOS Laser Driver  Transient response with line parasitics Current (A) Voltage (V)  Wirebonding : 2 nH  Soldering, cable : 10 nH  Trace line : 5 nH  Speed : 10 Gbps

Low Power CMOS Laser Driver  Decoupling capacitors

Low Power CMOS Laser Driver  Simulations with parasitics and decoupling capacitors Current (A) Voltage (V)  Input : 800 mV p-p PRBS  Speed : 10 Gbps  Mod. : up to 10 mA p-p  Power : 62.5 mW

Low Power CMOS Laser Driver  Temperature Variations Yellow : 27 o C Red : 100 o C Cyan : 200 o C Voltage (V) Current (A)

Low Power CMOS Laser Driver ESD protection circuitry MiM Capacitors Multiple finger structure A symmetrical layout Current density consideration  Layout of Laser Driver

Low Power CMOS Laser Driver Transimpedance amplifier Laser Drivers Calibration transistors  TSMC 0.18um Chip Layout

Low Power CMOS Laser Driver Positive ESD Pulse are clamped to the ESD_VDD Negative ESD pulse are clamped to the ESD_VSS  ESD protection circuitry

Low Power CMOS Laser Driver  Test Setup

Low Power CMOS Laser Driver  Test board Transmission characteristics (S21) of the traces on the test board using HPADS Frequency (Hz) S(21) dB 5 GHz10 GHz -5 dB -2 dB

Low Power CMOS Laser Driver  Transient response 1 Gbps Error-Free 5 Gbps

Low Power CMOS Laser Driver  Transient response test 3.11 x BER at Gbps

Low Power CMOS Laser Driver  SONET OC-192 eye mask

Low Power CMOS Laser Driver  Simulation vs. Measurement  Simulation  Measurement

Low Power CMOS Laser Driver SpecificationsConditions Laser modulationup to 12 mA Power Dissipation65.5W Speedover 10 Gbps BER> 3.11 X Area825 X 613 μm TechnologyTSMC 0.18 μm CMOS  Optimized specifications of the laser driver

Low Power CMOS Laser Driver AuthorsSpeedModulationBiasInputTechnology Chan G.C2.5 Gbps20 mAp-p10 mA800 mVp-p0.35 um Chan C.T2.5 Gbps20 mAp-pN/A 0.18 um CMOS Petersen A. K10 Gbps30 mAp-p40 mA500 mVp-p0.18 um CMOS Cao, J10 Gbps8 mAp-pN/ALVDS0.18 um CMOS Eo, J.Y10 GbpsN/A 250 mVp-pInGaP HBT Alexandru A.C10 Gbps20 mAp-p10 mA400 mVp-pSiGe HBT  Published laser drivers

Low Power CMOS Laser Driver  A detailed comparison Low power consumption Up to 12 Gbps operation The lowest input voltage SpeedMod.InputPower Eo’s work10 GbpsN/A250 mV65 mW Petersen’s work10 Gbps30 m500 mV492.2 mW This research12 Gbps10 m800 mV65.5 mW This research10 Gbps40 m100 mV312 mW

Thin Film Laser Integration onto CMOS Circuits 20 mA0 mA developed by GT optoelectric group  Edge emitting laser

Thin Film Laser Integration onto CMOS Circuits  Thin film integration  Separate fabrication  Independent optimization  Reduce packaging parasitics

Thin Film Laser Integration onto CMOS Circuits  Metal line experiments 500 um length and 20 um spacing b/w lines 3 um SiO 2 on a silicon substrate S(21) dB

Thin Film Laser Integration onto CMOS Circuits  A photograph of the fabricated optical transmitter

Thin film Laser integration onto CMOS chip  Simulation  L-I measurement  Simulation and Measurement

Conclusion and Future Work  High-speed and low power CMOS laser driver was designed and tested  High-speed laser diode and parasitics in packaging were modeled and incorporated in the driver design  Low power consumption at 10 Gbps speed  The driver compatible with LVDS IEEE standard was designed, simulated  The first demonstration of thin film laser onto CMOS laser driver

Conclusion and Future Work  Future Work Speed verification of the optical transmitter with a thin film laser Additional function blocks such as a multiplexer Verification of high-current LVDS driver circuitry Implementation of optical transceiver with optical receivers.

Questions