PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS BARIS TASKIN AND IVAN S. KOURTEV UNIVERSITY OF PITTSBURGH DEPARTMENT OF ELECTRICAL ENGINEERING

Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

Introduction Large-scale SOC Time borrowing (cycle stealing) Clock skew scheduling Clock/Timing schedule Minimum clock period

Local data path Graph Background

Latch Operation Positive level-sensitive

Time Borrowing Flip-Flop basedLatch based Higher Operating Frequency! 0.5 T  Data Propagation  T0.5 T  Data Propagation  1.5 T

Clock Skew T skew (i,f) = t i - t f Clock signal delay at the initial register Clock signal delay at the final register

Clock Skew Scheduling Zero clock skew Non-zero clock skew Higher Operating Frequency! 0.5 T  Data Propagation  T 0.5 T + T SKEW  Data Propagation  T + T SKEW

Optimization Problem Flip-flop-based Zero clock skew Latch-based Non-zero clock skew Time borrowing + Clock skew scheduling 0.5 T  Data Propagation  T 0.5 T + T SKEW  Data Propagation  1.5 T + T SKEW

Timing Parameters

Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

Constraints 1. Latching 2. Synchronization 3. Propagation 5. Skew CLOCK SKEW Constant or Variable? 4. Validity

Latching Constraints afaf AfAf

Synchronization Constraints

Max!

Propagation Constraints Min ! Max !

Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

Problem Formulation Timing constraints  NLP problem  Equivalent LP model Modified big M Method

Modified big M (MBM) Method min Z  min (Z+Ma) a=max (b,c)  a  ba  ca  ba  c min Z  min (Z-Ma) a=min (b,c)  a  ba  ca  ba  c

MBM Method Example Obj: Min Z= 5a+4b s.t. c C1 : c=max(a,b) C2 : a=3 C3 : b=7 NON-LINEAR a bc M c C1a: c  a C1b: cb +1000c LINEAR

LP Model Formulation [Synchronization Constraint-I]

Implementation and Model Highlights C++ implementation Off-shelf optimizer (CPLEX) Provide stand-alone model –Robust, fast –Sensitivity analysis

Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

Timing Analysis CIRCUIT TOPOLOGY CLOCKING METHODOLOGY MAX OP. FREQUENCY TIMING SCHEDULE CLOCKING SCHEDULE SENSITIVITY * INPUT OUTPUT

Example

R1 R3 R2 R4 R5 Circuit C Clock Pin... Additional Constraints t R1 = t R4 = c c:constant Clock signal delays at R 1 and R 4

ISCAS’89 Benchmark Results CIRCUIT INFORMATION NON-ZERO SKEW SCHEDULING CONSTRAINED CIRCUIT Circuit No of registers No of data paths TimeI3I3 I4I4 s s38% s s41% s s63%23% s s39% s s31% Average---27%24% TIME BORROWING  15% CLOCK SKEW SCHEDULING  14% SIMULTANEOUS  27%

Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

Increased performance Time borrowing Clock skew scheduling Complete framework for timing analysis Multi-phase synchronization

PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS BARIS TASKIN AND IVAN S. KOURTEV QUESTIONS UNIVERSITY OF PITTSBURGH DEPARTMENT OF ELECTRICAL ENGINEERING