CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicE: Clock Skew and Clock Gating José Nelson Amaral
CMPUT Computer Organization and Architecture II2 Timing With Propagation Delays
CMPUT Computer Organization and Architecture II3 Clock Skew yClock signal may not reach all flip-flops simultaneously. yOutput changes of flip-flops receiving “early” clock may reach D inputs of flip-flops with “late” clock too soon.
CMPUT Computer Organization and Architecture II4 Clock Skew Reasons for slowness: (a) wiring delays (b) capacitance (c) incorrect design
CMPUT Computer Organization and Architecture II5 Clock-skew calculation t ffpd(min) + t comb(min) t hold t skew(max) > 0 xFirst two terms are minimum time after clock edge for a D input to change xHold time is earliest time that the input may change xClock skew subtracts from the available hold-time margin xCompensating for clock skew: Longer flip-flop propagation delay Explicit combinational delays Shorter (even negative) flip-flop hold times
CMPUT Computer Organization and Architecture II6 Example of bad clock distribution
CMPUT Computer Organization and Architecture II7 Clock distribution in ASICs zThis is what a typical ASIC router will do if you don’t lay out the clock by hand.
CMPUT Computer Organization and Architecture II8 “Clock-tree” solution xOften laid out by hand xWide,fast metal (low R ==> fast RC time constant)
CMPUT Computer Organization and Architecture II9 Gating the clock yDefinitely a no-no xGlitches possible if control signal (CLKEN) is generated by the same clock xExcessive clock skew in any case.
CMPUT Computer Organization and Architecture II10 If you really must gate the clock...