Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 4 Introduction to Computer Organization

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter Outline System OrganizationSystem Organization CPU OrganizationCPU Organization Memory Organization and InterfacingMemory Organization and Interfacing I/O Organization and InterfacingI/O Organization and Interfacing Relatively Simple ComputerRelatively Simple Computer 8085-based Computer8085-based Computer

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Basic Computer Organization

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 System Components CPU/MicroprocessorCPU/Microprocessor Memory SubsystemMemory Subsystem I/O SubsystemI/O Subsystem

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 System Buses Address BusAddress Bus Data BusData Bus Control BusControl Bus

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of I/O Organization Isolated I/OIsolated I/O Memory-mapped I/OMemory-mapped I/O

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Types of Memory Static RAMStatic RAM Dynamic RAMDynamic RAM ROMROM PROMPROM EPROMEPROM EEPROMEEPROM

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Combining Memory Chips to Increase Word Size

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Combining Memory Chips to Increase Address Space

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Low-order Interleaving

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 von Neumann Architecture Instructions and data mixedInstructions and data mixed Used in modern computersUsed in modern computers

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Harvard Architecture Instructions and data separateInstructions and data separate Used in low-level cache memory designUsed in low-level cache memory design

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Big Endian Data Organization Most significant byte firstMost significant byte first

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Little Endian Data Organization Least significant byte firstLeast significant byte first

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 I/O Interface Enhancements READY signalREADY signal InterruptsInterrupts DMADMA

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Relatively Simple Computer Specifications Relatively Simple CPURelatively Simple CPU 8K ROM starting at 0000H8K ROM starting at 0000H 8K RAM starting at 2000H8K RAM starting at 2000H Memory-mapped, bidirectional I/O port at 8000HMemory-mapped, bidirectional I/O port at 8000H

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Relatively Simple Computer Organization - Memory Details

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 INCLUDE EXTERNAL ANIMATION FROM JAVA SIMULATOR HERE

Images courtesy of Addison Wesley Longman, Inc. Copyright © based Computer Specifications 2K EPROM starting at 0000H2K EPROM starting at 0000H 256 bytes RAM starting at 2000H256 bytes RAM starting at 2000H Four 8-bit I/O ports at 00H, 01H, 19H, and 1AHFour 8-bit I/O ports at 00H, 01H, 19H, and 1AH One 6-bit I/O port at 1BHOne 6-bit I/O port at 1BH

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Demultiplexing the AD signals

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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Summary Basic Computer OrganizationBasic Computer Organization CPU OrganizationCPU Organization Memory Chip Internal OrganizationMemory Chip Internal Organization Memory Subsystem OrganizationMemory Subsystem Organization I/O Port Organization and InterfacingI/O Port Organization and Interfacing