A Modified Rijndael Algorithm and it’s Implementation on FPGA Information Engineering & Technology German University In Cairo Department of Electronics and Electrical Engineering A Modified Rijndael Algorithm and it’s Implementation on FPGA Ahmed Abou-Bakr Mohamed Electronics Dept., Information Engineering & Technology German University in Cairo (GUC) Dr. Ahmed Hasan Madian Assistant Professor, Electronics Dept.,

Outline Introduction Rijndael Algorithm Implementation Modified Rijndael Implementation results Conclusion Dr. Ahmed H. Madian

Introduction In 1998 the DES has been expired as security algorithm National Institute of Standards and Technology (NIST) initiates a process to develop an Advanced Encryption Standard (AES) On November 26, 2001 NIST announced that the Rijndael encryption algorithm became the AES 3

Rijndael Developed by two Belgian cryptographers where it’s based on SP-Networks. The ciphering process is divided into three stages: Key Expansion Rounds Final Round C. Chitu and M. Glesner, An FPGA implementation of the AES-Rijndael in OCB/ECB modes of operation, Microelectronics Journal 36 (2005) 139146, 21 October, 2004. RIJNDAEL BLOCK DIAGRAM

1- Substitution It’s a non linear operation were 128 bit data is broken down into 16 chunks, 8 bits each, each of which is used as the address for S-box look up table.

1- Substitution (cont’d) Substitution Simulation

2- Inverse Substitution Inverse Substitution Simulation

3- Shift Rows Cyclically permutes the rows of the input data to the left.

3- Shift Rows (cont’d) Shift Rows Simulation

4- Inverse Shift Rows Cyclically permutes the rows of the input data to the right.

4- Inverse Shift Rows (cont’d) Inverse Shift Rows Simulation

5- Mixing Columns P • S S’ = Computes a new matrix S' by multiplying two matrices together the current matrix S by the polynomial matrix P. 2 3 1 S11 S12 S13 S14 S21 S22 S23 S24 S31 S32 S33 S34 S41 S42 S43 S44 S’ =

5- Mixing Columns (cont’d) Multiplication By ‘1’: The Data remains the same. Multiplication By ‘2’: The 8 bit data is left shifted by 1 bit. The least significant bit is replaced by 0. Then the most significant bit of the original data is used for comparison (a) If it is 0, then the left shifted data is the result. (b) If it is 1, then the left shifted value is XORed with the reduction polynomial, which in our case is 00011011, to generate the result.

5- Mixing Columns (cont’d) Multiplication By 2 Simulation Multiplication By ‘3’: We simply XOR the original input with the result of multiplication by 2.

5- Mixing Columns (cont’d) Mixing Columns Simulation

7- Key Expansion One of the functions that ensures that a cryptography algorithm is not vulnerable. Generates ten matrices using the round constant matrix. The key expansion process is divided mainly into three operations: Rotation Substitution Xoring

7- Key Expansion (cont’d) Rotation: Rotates a 32 bit input one byte to the left. Substitution: Similar to the one described above. Xoring: Bit wise xor operation of corresponding bits.

7- Key Expansion (cont’d) Row 6 contains the results from xoring row 5 and row 2 together. To get row 5, row 4 is rotated, substituted and the xored with row 1 of the round constant matrix. Finally the output of such an operation is then xored with row 1 to get row 5.

7- Key Expansion (cont’d) During the implementation only one matrix was generated, due the delay that will be caused since that each new row depends on the previous one. Key Expansion Simulation

8- Round Key Addition It simply performs a bit wise xor operation of the expanded round key with another input.

8- Round Key Addition (cont’d) Round Key Addition Simulation

Modified Rijndael Algorithm

9- Proposed Stage Of Modified Rijndael Mirror Inverse Mirror Doesn’t require any arithmetical or logical operations thus routing was used during implementation.

9- Proposed Stages for Rijndael Modification (cont’d) Mirror Simulation Inverse Mirror Simulation

10- Encryption / Decryption

10- Encryption / Decryption (cont’d) Encryption / Decryption FSM

10- Encryption / Decryption (cont’d)

Implementation results Category Used Total Available % Used Slice Flip Flops 3658 18816 19% Slices 7148 9408 75%

Conclusion Modified Rijndeal algorithm has been presented The modification done with adding new stage mirror stage which doesn’t require bigger hardware area. The system has been simulated and implemented on FPGA with total area of 75% and max. frequency of 44MHz.

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