FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element –Xilinx CLB –Altera LE n Interconnection n Configuration

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGAs n Program logic functions, interconnect using SRAM. n Advantages: –Re-programmable –dynamically reconfigurable –uses standard processes n Disadvantages –SRAM burns power. –Possible to steal, disrupt configuration bits

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM Based Logic element n Logic element – includes combinational function + register(s). n Use SRAM as lookup table – for combinational function.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR LUT-based logic element Lookup table configuration bits out inputs Can multiplex at output or address at input n 1

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Evaluation of SRAM-based LUT n N-input LUT –can handle function of 2 n inputs. n All logic functions – take the same amount of space. n All functions – have the same delay. n SRAM is larger – than static gate equivalent of function. n Burns power – at idle. n Selectively –add register to LE

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Registers in logic elements n Register may be selected into the circuit: LUT DQ Configuration bit LE out

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Other LE features n Multiple logic functions in an LE n Addition logic –carry chain. n Partitioned lookup tables

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Xilinx Spartan-II CLB n Each CLB has two identical slices. n Slice has two logic cells: –LUT. –Carry logic. –Registers.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II CLB details n Each lookup table can be used as a 16-bit synchronous RAM or 16-bit shift register. n Arithmetic logic includes an XOR gate. n Each slice includes a mux to ocmbine the results of the two functino generators in the slice. n Register can be configured as DFF or latch. n Has three-state drivers (BUFTs) for on-chip busses.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II CLB operation n Arithmetic: –Carry block includes XOR gate. –Use LUT for carry, XOR for sum. n Each slice uses F5 mux to combine results of multiplexers. n F6 mux combines outputs of F5 muxes. n Registers can be FF/latch; clock and clock enable. n Includes three-state output for on-chip bus.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Altera APEX II logic element n Each logic array block has 10 logic elements. n Logic elements share some logic.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Apex II LE modes n Modes of operation: –Normal. –Arithmetic. –Counter.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR APEX-II LE normal mode

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR APEX-II LE arithmetic mode

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR APEX-II LE counter mode

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR APEX-II LE control logic

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Programmable interconnect n MOS switch –controlled by configuration bit DQ

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Programmable vs. fixed interconnect n Programmable interconnect –Switch adds delay. –Transistor off-state is worse in advanced technologies. –FPGA interconnect has extra length = added capacitance.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Interconnect strategies n Some wires – will not be utilized. n Congestion will not be same –throughout chip n Types of wires: –Short wires »local LE connections. –Global wires »long-distance, buffered communication. –Special wires »clocks, etc.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Paths in interconnect n Connection may be long, complex: LE Wiring channel

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Interconnect architecture n Type of connection –Connections from wiring channels to LEs. –Connections between wires in the wiring channels. LE Wiring channel

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Interconnect richness n Within a channel –How many wires. –Length of segments –Connections from LE to channel n Between channels –Number of connections between channels –Channel structure

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Switchbox channel

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II interconnect n Types of interconnect: –local; –general-purpose; –dedicated; –I/O pin.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II general-purpose network n Provides majority of routing resources: –General routing matrix (GRM) »connects horizontal/vertical channels and CLBs. –Interconnect » between adjacent GRMs. –Hex lines »connect GRM to GRMs six blocks away. –12 longlines »span the chip

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II routing n Relationship between GRM, hex lines, and local interconnect

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II three-state bus n Horizontal on-chip busses:

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II clock distribution

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR APEX II interconnect column row

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II I/O n Supports multiple I/O standards –LVTTL, PCI, LVCMOS2, AGP2X, etc. n Provides registers. n Programmable delay for pin-dependent hold time. n Programmable weak keeper circuit.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II I/O block diagram

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Configuration n Need to set all configuration SRAM bits –minimum pin cost; –reasonable speed. n Configuration can also –be read back for testing

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Configuration ROM n Configured on start-up from ROM: FPGA Configuration memory

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Spartan-II configuration n Configuration length – depends on size of chip »200,000 to 1.3 million bits. n Configuration modes –Master serial »for first chip in chain. –Slave serial »for follow-on chips. –Slave parallel –Boundary-scan

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Scan chain n Scan chain –shift register used to access internal state. n Logic-sensitive scan design (LSSD) – scan structure that uses some hardware for normal mode and scan.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR JTAG boundary scan n JTAG –Joint Test Action Group. n Boundary scan –provide scan chain at pins –allow control of chip interior –decouple chip from rest of board for test

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Chip-on-board testing n Boundary scan decouples chips: board

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Boundary scan concepts n TAP: test access port. –Requires three pins not shared with other logic. –Test reset, test clock, test mode select, test data in, test data out. n TAP controller –recognizes pins, controls boundary scan registers. n Instruction register –defines boundary scan mode.