IBIS FUTURES COMMITTEE MULTILINGUAL MODEL: DIGITAL PORT ISSUES Ian Dodd 25 th March 2004

ICD, Multiligual Model: Digital Port Issues, 25th March 2004 Non Company Confidential 2 n Standard Digital Ports: — Inputs n D_enable n D_drive — Outputs n D_receive Digital Multilingual Ports

ICD, Multiligual Model: Digital Port Issues, 25th March 2004 Non Company Confidential 3 n VHDL-AMS and Verilog-AMS port types must match exactly between the SI tools top level circuit and user multilingual model. n It is assumed we will ensure this by requiring model providers to use standard port types: — It is assumed the reference to IEEE Std_logic_1164 enforces one (9 state) digital port type for VHDL- AMS — We need to specify something equivalent for Verilog- AMS digital ports — Do we need to also specify port type/nature for analog ports. Digital Port Type Concerns

ICD, Multiligual Model: Digital Port Issues, 25th March 2004 Non Company Confidential 4 n Propose we limit the logic states that are legal for the standard digital ports: — Inputs n VHDL-AMS ‘1’, ‘0’ or Verilog-AMS equivalent — Outputs n VHDL-AMS ‘1’, ‘X’, ‘0’ or Verilog-AMS equivalent Allowed Digital Logic Levels

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