Feng-Xiang Huang MCORE Architecture implements Real-Time Debug Port based on Nexus Consortium Specification David Ruimy Gonzales Senior Member of Technical.

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Feng-Xiang Huang MCORE Architecture implements Real-Time Debug Port based on Nexus Consortium Specification David Ruimy Gonzales Senior Member of Technical Staff Motorola MCORE TM Technology Center Austin, Texas 2015/5/23

Combining Scan and Trace Buffers for Enhancing Real-time Observability in Post-Silicon Debugging 2010 Combining Scan and Trace Buffers for Enhancing Real-time Observability in Post-Silicon Debugging 2010 A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains 2010 A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains 2010 NIFD: Non-Intrusive FPGA Debugger Debugging FPGA ‘Threads’ for Rapid HW/SW Systems Prototyping 2010 NIFD: Non-Intrusive FPGA Debugger Debugging FPGA ‘Threads’ for Rapid HW/SW Systems Prototyping 2010 A Design-for-Debug(DfD) for NoC-based SoC Debugging via NoC 2008 A Design-for-Debug(DfD) for NoC-based SoC Debugging via NoC 2008 A Low-Cost SOC Debug Platform Based on On- Chip Test Architectures 2009 A Low-Cost SOC Debug Platform Based on On- Chip Test Architectures 2009 A High-Level Debug Environment for Communication-Centric Debug 2009 A High-Level Debug Environment for Communication-Centric Debug 2009 Exploiting an I-IP for both Test and silicon Debug of Microprocessor Cores 2005 Exploiting an I-IP for both Test and silicon Debug of Microprocessor Cores 2005 Scan applicationDebug IPHW/SW IEEE JTAG Nexus 5001 Forum TM Standard

For Tool Vendors Highly integrated How Programs flow Tradeoff between Performance & Visibility Difficult Offer consistent functionality across architecture to tool venders

What’s Nexus  Nexus is standard, real-time interface for embedded process. 。 On-chip debug features 。 Protocols 。 Pin 。 Interface to externals tool  Companies: Motorola, Siemens, Hitachi, …,24 companies anticipated. Nexus provides a toolbox of features for processor debug  Support existing debug interface JTAG  Auxiliary trace debug interface  Simple packet based message protocol  Define classed for standard with increasingly complex implement

Real-time information Variable Levels Static debug Dynamic debug

A Scalable Port EVTI: Nexus Event Input EVTO: Nexus Event Output MSEO: Nexus Message Start/End Output MCKO: Nexus Message Clock Output MDO: Nexus Message Data Output RDY: Nexus Ready Output

 Half duplex  Full duplex More Complexity  High Performance Class 1: Compliancy JTAG Basic Run-Control Class 1: Compliancy JTAG Basic Run-Control Class 2,3,4: Auxiliary debug interface Class 2,3,4: Auxiliary debug interface Static debug features dynamic debug features  Variable Message-based  Simple trace compress  Variable Message-based  Simple trace compress

Packet-based data  Monitoring Program Flow 。 Ownership Message: process identification 。 Branch Trace Message: program counter’s change of flow 。 Watchpoint Message:  Data Trace Messages 。 Reporting real-time specific data accesses to memory location  Memory substitution Messages 。 Emulate a bus where opcodes and data may be accessed.  Auxiliary Access Messages 。 Read/Write auxiliary control and status registers.

The first implementation of this proposed standard Low pin count Low power consumption OnCE TM debug block  JTAG protocol  Limited observation of real-time program flow

Auxiliary interface JTAG interface 16 Deep FIFO Real-time Message 16 Deep FIFO Real-time Message Class 1

Class levels classified  a scalable debug  needs for specific debug stages Standardize on a set of features, protocols…, etc.  Rapid development of real-time microcontroller based products. 。 Time to Market  It is Benefit of tool Vendors, providing an standardized on a set of features.

It is benefit not only tool vendors, but designer. It emphasizes the message of Nexus defined, not talks more detail about protocol of Auxiliary interface.  FIFO design of control protocol is key using by auxiliary port, Message format also is.