June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology PAR ERROR: ◦ ERROR:Place: A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock IOB component is placed at site. The corresponding BUFGCTRL component is placed at site. The clock IO can use the fast path between the IOB and the Clock Buffer if the IOB is placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in its half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the.ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the.ucf file to override this clock rule. PAR Error: 2

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Cause: RESET is connected to a “N” type Single Region Clock Capable (SRCC) pin. As the design grows, one needs to use the top & bottom part of the FPGA. Only “P” side pins can drive global clock nets. We already had this issue for CLK20_VCXO ◦ see slide 14: ◦ 0.pptx 0.pptx Solution: Swap FPGA pins for NRESET and RESET (note: NRESET connects to “P”) PAR Error: 3

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Vincent ran into memory limitations ◦ always the same story with these memory hungry software engineers… Increased from 88 Kbytes to 128 Kbytes ◦ BMM files for XST and Precision changed but nobody should have noticed this… LM32_2 nd Memory: 4

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology With higher TDC rates in rare conditions… Missing either 1, 2 or 3, 16-bit words randomly Checksum: “unchecked, not all data available” UDP Length error: 5

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Who is to blame? ◦ TDC + StateMachine (unlikely)  It just forwards payload that will be counted by IPMUX ◦ IPMUX (unlikely)  The correct length word (counted by IPMUX) is in the header so IPMUX must have seen all data words… ◦ The interface between IPMUX and WR (maybe) ◦ WR endpoint (maybe) UDP Length error:

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Test to hunt for the UDP Length error: 7 Added UDP Length checker. Verification signalling (to Oscilloscope): Length Okay Length Error Test packet generator: 16 x okay 0 x error

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Test to hunt for the UDP Length error: 8 Only okay’s 0 triggers on error Conclusion: Up to the WRPC input all is okay! Focus on WRPC (endpoint)

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Further points checked: 9 Input ep_tx_frames (= WR MAC) Input 1000basex-PCS Input PHY All okay!? I must be doing something wrong… ◦ Sorry… Got the wrong file updated. ◦ => work in progress.

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology While hunting down the UDP Length error issue: I had a simulation stall. IPMUX connects to the non empty input fifo of the TDC channel and starts reading packet payload. It keeps connected (there is no other way) until it completes the payload transfer (i.e. EOD). When for some reason no EOD is generated (or it takes a while, i.e. one time slice) then it keeps waiting, effectively blocking other inputs. Example case study: ◦ Long time slice with no data IPMUX is connected to TDC for the time slice duration ◦ During this time AES data should be buffered IPMUX arbitration 10

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Three parameters to optimize the dataflow: 1.Proper setting for the packet size. 2.Buffer sizes (either the TDC/AES fifos or the IPMUX input fifo) can help optimize the dataflow. 3.The arbitration scheme. Now all channels are served equally so one has to wait for the other. For the time being I see no problems but we should be aware of this behaviour! IPMUX arbitration 11

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Tommaso proposed to have no TDC-UDP data packets if there is no TDC data in the Time Slice. Do we want that behaviour? ◦ If we don’t send data each Time Slice (even if it is empty) then the DAQ cannot distinguish between data that is still in the pipeline or apparently the time slice was empty. => a timeout is needed. ◦ Sending an Time Slice packet that contains no TDC data at least tells the DAQ that it can continue with data processing. No timeout. Empty Time Slice to DAQ? 12

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology ½ DOM electronics + readout EMC Climate Rate test Golden image ◦ Golden image reprogrammable itself? => Test! ◦ SFP wave length shift  Test: unplug CLB Tx fiber and see if we can switch a LED on/off (i.e. without upstream communication) PRR 13

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Pause frame implementation ◦ Gave some feedback to TIPP2014 ◦ Feedback 7-Sols to WR community? Calibration. Yes/no WR in the DOMs ◦ WR very handy for Dark Room Calibartion! ◦ Also handy for Dark Room Calibartion: Make PPS signal available with an assembled DOM (RF? Via Nano-Beacon?) Other topics that keep me busy 14 DU-Base WR- Calibrator Measure strings “constant” delays (to be considered as delta Rx for each of the DOMs)

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Backup slides 15

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Zoom into WRPC: 16 Added UDP Length checker. Verification signalling (to Oscilloscope): Length Okay Length Error Again: Only okay’s 0 triggers on error

June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Zoom into WRPC endpoint: 17 okay Again: Only okay’s 0 triggers on error Ep_tx_framer snktxpcs_fabphy_tx Wr_gtx_phy_kintex7 okay ep_tx_pcs_16bit ep_1000basex_pcs serdes_tx pcs_fab errors