Architecture Design Methodology. 2 The effects of architecture design on metrics:  Area (cost)  Performance  Power Target market:  A set of application.

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Presentation transcript:

Architecture Design Methodology

2 The effects of architecture design on metrics:  Area (cost)  Performance  Power Target market:  A set of application circuits to be attempted

3 Methodology

4 Aspects of an experimental flow 1.The depth of the CAD flow:  Synthesis, packing, placement, and routing  The deeper the CAD flow, the more precise and believable the results.  More effort and computation time. 2.The quality of the CAD tools used:  Low-quality tools can give misleading architectural results.  Use the best tools available in CAD flows 3.The set of benchmark circuits used:  How representative the benchmark circuits are w.r.t. typical circuits. 4.The quality of the models:  Simple or accurate models? 5.The quality of analysis tools:  Simple or accurate analyzers?

5 Example Area-granularity experiment:

6 Example Observations:  As the LUT size (K) increases, the number of LUTs required to implement the circuits significantly decreases.  The area required for each block increases significantly: Justification for area increase: 1.# of programming bits in a K-input lookup table is 2 K. 2.# of transistors in the LUT increases. 3.# of pins connecting into the logic block increases.  # of routing tracks surrounding the logic required for successful routing increases.

7

8 Example Product of two curves:  Total area.

9 Hierarchical Structure Basic Logic Element (BLE) Logic Cluster - Instead of growing LUT size: Hierarchical - Commonly used in most industrial FPGAs Local interconnect

10 Speed Trade-Offs Increase in functionality of the logic block  Fewer logic blocks are used on the critical path −  Fewer logic levels needed −  Higher overall speed  Its internal delay increases

11 Speed Trade-Offs  BLE = LUT in this figure [Ahmed06]

12 Speed Trade-Offs Total FPGA delay as a function of LUT size includes the routing delay  Recent trends in commercial architectures have indeed moved toward larger LUT sizes to capture these gains: −Altera Stratix III, IV −Xilinx Virtex 5, 6

13 Virtex 5, Virtex 6

14 Stratix IV

15 Power Trade-Offs Experiments:  The best logic block architectures for area are also the best logic block architectures for power consumption.  For a fixed, standard 4-LUT architecture: −Sleep transistors and threshold voltage settings achieve significant power consumption reductions.

16 PLA/PAL-Style Logic Blocks [Cong05]:  Fairly small PAL-like structure:  With 7–10 inputs  10–13 product terms −Performance gains (up to 33%) −Excessive area (27%) −Excessive power

17 PLA/PAL-Style Logic Blocks [Cong05]:  Another routing architecture −Performance gains (up to 27%) −Area reduction (17%) −Excessive power

18 References [Kuon07] I. Kuon and J. Rose, “Measuring the gap between FPGAs and ASICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 203–215, [Ahmed01] E. Ahmed, The Effect of Logic Block Granularity on Deep-Submicron FPGA Performance and Density. Master’s thesis, University of Toronto, Department of Electrical and Computer Engineering, [Xilinx] [Altera] [Cong05] J. Cong, H. Huang, and X. Yuan, “Technology mapping and architecture evaluation for k/m-macrocell-based FPGAs,” TODAES, vol. 10, pp. 3–23, January 2005.