Yan-Yu Huang, 2013 IEE5008 –Autumn 2013 Memory Systems NAND Flash Memory Controller Yan-Yu Huang Department of Electronic Engineering National Chiao Tung University, Hsinchu, Taiwan, R.O.C.

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Outline Introduction Overview of a Basic Controller Structure Flash Translation Layer Multichip Parallelism in Flash memory A variety of Different Architectures Controllers Conclusion Reference 2

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Introduction Improve chip performance Bit-flipping errors Bad blocks Increase battery life Reduces the CPU load on the device Do the operation independently Increases the overall throughput Reduce the load on the system 3

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Introduction Integrated controller Smaller chip size Cheaper cost Inevitable delay between a new Flash technology Dedicated or External controller Sourced independently of other parts. More flexible design Cost more money 4

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Overview of a Basic Controller Structure Host may be a computer or a terminal. FTL translates host request into flash request. Controller decide what time and which chip should work. Flash chip do read, write page or erase block. 5 Flash Controller FTL Host

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Flash Translation Layer ( FTL ) Maintain a mapping between logic address and physical address. Page level  One logical sector maps one physical block.  More flexible  Requires a large amount of memory for mapping table. Block level  One logical block maps one physical block.  It requires extra flash operations when only a few pages in a logical block are modified. 6

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Flash Translation Layer ( FTL ) A basic structure of FTL Garbage Collection Bad Block Management Error Checking and Correcting Wear Leveling Low Level Driver 7 Flash Controller FTL Host

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Garbage Collection Collect the valid data from the scattered blocks 8

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Low Level Driver Provide basic operation. That executes the operation directly on NAND Flash memory device.  Read  Write  Erase 9

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Error Checking and Correcting ( ECC ) That can detect and correct the most common kinds of internal data corruption. Maintains a memory system immune to single-bit errors. 10 N: the number of bits of a block E : the number of errors in a block P : the bit error rate

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Wear Leveling Maximizes the life span of NAND flash as each cell is used evenly. Static Dynamic 11

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Wear Leveling Implementing static wear leveling. All good blocks are evenly distribute the wear. With an additional step Implementing dynamic wear leveling. Select the one with the lowest erase count for the next write Only the non-static part of array is wear-leveling 12

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Bad Block Management ( BBM ) Perform write verification and remapping to spare sectors in case of write failure. 13

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Bad Block Management ( BBM ) Skip Block Method With a bad block table when the target address is address of bad block then chose the next. Reverse Block Method re-directed to a 14 Reserved Block Area

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Multichip parallelism in Flash memory Flash memory management High data accessing speed Chip-level Bus-level 15 Flash Controller FTL Host

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Multichip parallelism in Flash memory Chip-level Increase the effective bandwidth of flash operations. Maximum bandwidth is limited by the bus. 16

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Multichip parallelism in Flash memory Bus-level Parallel flash operation can across chips by different flash bus. Cost more area than chip-level. 17

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 A variety of Different Architectures Controllers Chip-level For FPGA application Bus-level & Chip-level Scalable Multi-channel Parallel Controller 18 Flash Controller FTL Host

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Controller for FPGA Application Provides a main state-machine with an enhance command. 19 System reset Enable signal Sub-state machine Interrupt signal timing sequences Reverse Block Method

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable Multi-channel Parallel Controller Multi-channel parallelism 20 Addressed uniformly state

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable Multi-channel Parallel Controller Switching fabric to implement the multi-channel parallel access mechanism. 21 Stored the request Select signal Data path The number of the request Data command address

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable Multi-channel Parallel Controller The single controller Main Control Module ECC Module 22 request Implement the control of flash operation control logic

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable Multi-channel Parallel Controller Main Control Module Core of the single controller with a main state machine. 23 Stored the data need to input or output request Main control logic Main state machine Sub-state machine Generate different control signal

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable Multi-channel Parallel Controller ECC Module Generates a ECC code of each page Detect the bit-flipping errors Modify one bit error 24 request Program page operation data ECC code Spare data area of the target chip

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Scalable Multi-channel Parallel Controller ECC Module Generates a ECC code of each page Detect the bit-flipping errors Modify one bit error 25 request read page operation Old code Bit-flipping error ? New code Address of error bit

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Conclusion Controller for FPGA Application Advantage  Without caring about the timing sequences  Replace the invalid block Disadvantage  Bit-flipping  Reliability The scalable Multi-channel Parallel Controller Advantage  Exploit the multi-chip parallelism to improve the bandwidth.  New dynamic replacing strategy for the mapping table. Disadvantage  For increase the bandwidth more channel will be needed. 26

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Conclusion Improve chip performance Handle the bit errors Bad blocks management Wear leveling High data accessing speed Flash memory management A well designed controller gets the maximum bandwidth of the NAND Flash device, whereas poorly designed one only reduces system performance. 27

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Reference [1] Jose, S.T., Pradeep, C., “Design of a Multichannel NAND Flash Memory Controller for Efficient Utilization of Bandwidth in SSDs”, 2013 International Multi-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), pp , Mar [2] Micron Technology, Inc. All Rights Reserved, (2013), Choosing the Right NAND, Retrieved 2013 Nov 30 form URL: [3] Yang Ou, Nong Xiao, Mingche Lai, “A Scalable Multi-channel Parallel NAND Flash Memory Controller Architecture”, 2011 Sixth Annual China Grid Conference, pp , Aug [4] Eyee Hyun Nam, Bryan Suk Joon Kim, Hyeonsang Eom, Sang Lyul Min, “Ozone (O3): An Out-of-Order Flash Memory Controller Architecture”, IEEE Transactions on Computers, vol. 60, no. 5, pp , May [5] Jose, S.T., Pradeep, C., “Design of a Multichannel NAND Flash Memory Controller for Efficient Utilization of Bandwidth in SSDs”, 2013 International Multi-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), pp , Mar [6] Chuan-Sheng Lin,Lan-Rong Dung, “A NAND Flash memory controller for SD/MMC flash memory card”, IEEE TRANSACTIONS ON MAGNETICS, vol. 43, no. 2, pp , Feb [7] Tang Lei, Zhou Xuan, Wu Yao, Li Jincheng, “Flash controller design for FPGA application”, ICEEE 2010 International Conference, pp. 1-4, Nov [8] Chanik Park, Prakash Talawar, Daesik Won, MyungJin Jung, JungBeen lm, Suksan Kim and Youngjoon Choi, “A high performance controller for NAND Flash-based solid state disk (NSSD)”, IEEE 21 st Non-Volatile Semiconductor Memory Workshop, pp , Feb [9] Y.J. Seong, E.H. Nam, J.H. Yoon, H. Kim, J.-y. Choi, S. Lee, Y.H. Bae, J. Lee, Y. Cho, nd S.L. Min, “Hydra: a block-mapped parallel flash memory solid-state disk architecture”, IEEE Transactions on Computers, vol. 59, no. 7, pp , Jul

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang, 2013 Reference [10] L.-P. Chang and T.W. Kuo, “An adaptive striping architecture for flash memory storage systems of embedded systems”, in Proceedings of the 8th Real-Time and Embedded Technology and Applications Symposium, San Jose, California, USA, pp , [11] N. Agrawal, V. Prabhakaran, T. Wobber, J.D. Davis, M. Manasse,and R. Panigrahy, “Design Tradeoffs for SSD Performance,” Proc.USENIX Ann. Technical Conf., [12] C. Dirik and B. Jacob, “The Performance of PC Solid-State Disks (SSDs) as a Function of Bandwidth, Concurrency, Device Architecture, and System Organization,” Proc. 36 th Int’l Symp.Computer Architecture, [13] Jin Hyuk Yoon, Eyee Hyun Nam, Yoon Jae Seong, Hongseok Kim, Bryan S. Kim, Sang Lyul Min, and Yookun Cho, “Chameleon: A High Performance Flash/FRAM Hybrid Solid State Disk Architecture”, IEEE Computer Architecture Letters, vol. 7, pp. 17, Jan [14] FUSION IO, ioDrive datasheet, [15] Denali, NAND Flash Controller IP,

NCTU IEE5011 Memory Systems 2013Yan-Yu Huang,