Evan Vaughan.  Get RTL Compilier and SoC Encounter to place & route a bitsliced datapath  Began by modifying/reducing libraries ◦ Modify>synthesize>P&R.

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Presentation transcript:

Evan Vaughan

 Get RTL Compilier and SoC Encounter to place & route a bitsliced datapath  Began by modifying/reducing libraries ◦ Modify>synthesize>P&R  Very time consuming and no good results.

 Original approach involved far too much custom design ◦ Abandoned that.  Focus has shifted to floorplanning  Use hierarchical design methodologies to floorplan

 Meant for large-scale designs ◦ By default, Encounter only makes it available for larger designs  Breaks design into manageable pieces when floorplanning  Allows for parallel design of blocks

 First must make a hierarchical design ◦ Original Kogge-Stone verilog completely flat  Modified verilog to make overall design hierarchical

Flat Design Hierarchical Design

 Hierarchical design yields no difference in P&R

 Uses partitions, modules, groups, fences, etc…  Fence allows user to define spaces where standard cells will be placed ◦ Can specify modules as fences  Specify each bit module as a fence ◦ Place fences in core as bitslices ◦ Place cells in fences  Encounter wasn’t showing my bits as modules

 Defining black boxes creates instances of the modules  Can place modules by hand then place black boxes (Place>Standard Cells)  Remove black boxes (unspecifyBlackBox –keepPtn) ◦ Removes black boxes but leaves fence behind ◦ Can then place standard cells within module fences.

 Kind of a hack ◦ Can’t unspecifyBlackBox from GUI ◦ Multiple placements  Works fine as script but cumbersome in the GUI  Can ignore Black Box flow and directly specify fences in a script or in terminal ◦ Still no way for GUI-based flow ◦ Fences do not show up in floorplan view

 By default, Encounter requires >100 cells for a module to be displayed after import. ◦ Design>Preferences>Display Min. Floorplan Module Size to change this. ◦ Alternatively “setPreference MinFPModuleSize 0” in a script/terminal  Can easily place & resize modules into the core area ◦ Define them as fences ◦ Place standard cells

 Very easily implemented as a script  Fences prevent cells from moving outside of assigned rows ◦ Optimization can be run without destroying bitslice  Easily integrated into any flow

 No previous ASIC design ◦ Scripting ◦ Synthesis ◦ Place & Route ◦ Verilog  Hierarchical Design methodologies