Chapter 3 Basic Logic Gates Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

The AND Gate The output, X, is HIGH if input A AND input B are both HIGH See Figure 3-1 Truth Table - see Table 3-1 Boolean Equation X = A and B or X = AB Can have more than two inputs Number of combinations = 2N Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-1 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

The OR Gate The output at X will be HIGH whenever input A OR input B is HIGH or both are HIGH See Figure 3-5 Truth Table - see Table 3-3 Boolean Equation X = A + B Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-5 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Timing Analysis Timing Diagram Oscilloscope Logic Analyzer voltage versus time up to two Logic Analyzer state table up to 16 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Enable and Disable Functions turn ON see Figure 3-17 Disable turn OFF see Figure 3-18 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-18 Figure 3-17 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Using Integrated Circuit Logic Gates See Figure 3-20 Enable and Disable Pin Connections VCC and GND Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-20 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Introduction to Troubleshooting Techniques The procedure used to find the fault or trouble in a circuit. Logic Probe metal tip indicator lamp(s) Floating - open circuit, neither HIGH nor LOW Logic Pulser - provide digital signal to a circuit Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

The Inverter Used to complement or invert a digital signal See Figure 3-27 Truth Table - see Figure 3-27 Boolean Equation X = A Inversion bar NOT gate Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-27 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

The NAND Gate Same as the AND gate except that its output is inverted See Figure 3-29 Truth Table - see Table 3-6 Boolean Equation X = AB multiple inputs - the output is always HIGH unless all inputs go HIGH Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-29 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

The NOR Gate Same as the OR gate except that its output is inverted See Figure 3-36 Truth Table - see Table 3-8 Boolean Equation X = A + B Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-36 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Logic Gate Waveform Generation Repetitive waveform Waveform generator Johnson shift counter See Figure 3-43 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-43 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Using Integrated-Circuit Logic Gates Hex - six gates Quad - four gates Three-, four-, and eight-input configurations See Figures 3-60 and 3-61 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-61 Figure 3-60 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Summary of Basic Logic Gates and IEEE/IEC Standard Logic Symbols See Table 3-9 See Figure 3-65 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Figure 3-65 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Summary The AND gate requires that all inputs are HIGH in order to get a HIGH output The OR gate outputs a HIGH if any of its inputs are HIGH An effective way to measure the precise timing relationships of digital waveforms is with an oscilloscope or a logic analyzer Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Summary Beside providing the basic logic functions, AND and OR gates can also be used to enable or disable a signal to pass from one point to another There are several integrated circuits available in both TTL and CMOS that provide the basic logic functions Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Summary Two important troubleshooting tools are the logic pulser and the logic probe. The pulser is used to inject pulses into a circuit under test. The probe reads the level at a point in a circuit to determine is it is HIGH, LOW, or floating An inverter provides an output that is the complement of its input Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Summary A NAND gate outputs a LOW when all of its inputs are HIGH A NOR gate outputs a HIGH when all of its inputs are LOW Specialized waveforms can be created by using a repetitive waveform generator and the basic gates Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

Summary Manufacturer’s data manuals are used by the technician to find the pin configuration and operating characteristics for the ICs used in modern circuitry. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version