Assessing Chip-Level Impact of Double Patterning Lithography Kwangok Jeong , Andrew B. Kahng ,, and Rasit O. Topaloglu *

Slides:

Advertisements

Similar presentations

Hierarchical Dummy Fill for Process Uniformity Supported by Cadence Design Systems, Inc. NSF, and the Packard Foundation Y. Chen, A. B. Kahng, G. Robins,

Advertisements

(1/25) UCSD VLSI CAD Laboratory - ISQED10, March. 23, 2010 Toward Effective Utilization of Timing Exceptions in Design Optimization Kwangok Jeong, Andrew.

Design Rule Generation for Interconnect Matching Andrew B. Kahng and Rasit Onur Topaloglu {abk | rtopalog University of California, San Diego.

OCV-Aware Top-Level Clock Tree Optimization

-1- VLSI CAD Laboratory, UC San Diego Post-Routing BEOL Layout Optimization for Improved Time- Dependent Dielectric Breakdown (TDDB) Reliability Tuck-Boon.

Kwangok Jeong and Andrew B. Kahng UCSD VLSI CAD Laboratory

UCLA Modeling and Optimization for VLSI Layout Professor Lei He

Timing Margin Recovery With Flexible Flip-Flop Timing Model

Noise Model for Multiple Segmented Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu †, Niranjan A. Pol ‡ and Devendra Vidhani* UCSD CSE and ECE.

The Impact of Variability on the Reliability of Long on-chip Interconnect in the Presence of Crosstalk Basel Halak, Santosh Shedabale, Hiran Ramakrishnan,

Rasit Onur Topaloglu University of California San Diego Computer Science and Engineering Department Ph.D. candidate “Location.

Power-Aware Placement

Statistical Crosstalk Aggressor Alignment Aware Interconnect Delay Calculation Supported by NSF & MARCO GSRC Andrew B. Kahng, Bao Liu, Xu Xu UC San Diego.

Design Sensitivities to Variability: Extrapolations and Assessments in Nanometer VLSI Y. Kevin Cao *, Puneet Gupta +, Andrew Kahng +, Dennis Sylvester.

Impact of Guardband Reduction on Design Process Outcomes Kwangok Jeong Andrew B. Kahng Kambiz Samadi

Architectural-Level Prediction of Interconnect Wirelength and Fanout Kwangok Jeong, Andrew B. Kahng and Kambiz Samadi UCSD VLSI CAD Laboratory

Enhanced Resist and Etch CD Control by Design Perturbation Abstract Etch dummy features are used to reduce CD skew between resist and etch processes and.

Study of Floating Fill Impact on Interconnect Capacitance Andrew B. Kahng Kambiz Samadi Puneet Sharma CSE and ECE Departments University of California,

On Modeling and Sensitivity of Via Count in SOC Physical Implementation Kwangok Jeong Andrew B. Kahng.

Fast and Area-Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts Charles Chiang, Synopsys Andrew B. Kahng, UC San Diego Subarna.

April 16th, Photomask Japan 2008 Electrical Metrics for Lithographic Line-End Tapering Puneet Gupta 3,

DPIMM-03 1 Performance-Impact Limited Area Fill Synthesis Yu Chen, Puneet Gupta, Andrew B. Kahng (UCLA, UCSD) Supported by Cadence.

On-Line Adjustable Buffering for Runtime Power Reduction Andrew B. Kahng Ψ Sherief Reda † Puneet Sharma Ψ Ψ University of California, San Diego † Brown.

1 UCSD VLSI CAD Laboratory ISQED-2009 Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization Kwangok Jeong, Andrew.

Toward Performance-Driven Reduction of the Cost of RET-Based Lithography Control Dennis Sylvester Jie Yang (Univ. of Michigan,

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Sub-Micron Design Yu (Kevin) Cao 1, Chenming Hu 1, Xuejue Huang 1, Andrew.

A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield A. B. Kahng, B. Liu, X. Xu, J. Hu* and G. Venkataraman*

UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.

Lei He, Andrew B. Kahng*, Kingho Tam, Jinjun Xiong

Circuit Performance Variability Decomposition Michael Orshansky, Costas Spanos, and Chenming Hu Department of Electrical Engineering and Computer Sciences,

Detailed Placement for Leakage Reduction Using Systematic Through-Pitch Variation Andrew B. Kahng †‡ Swamy Muddu ‡ Puneet Sharma ‡ CSE † and ECE ‡ Departments,

Defocus-Aware Leakage Estimation and Control Andrew B. Kahng †‡ Swamy Muddu ‡ Puneet Sharma ‡ CSE † and ECE ‡ Departments, UC San Diego.

Topography-Aware OPC for Better DOF margin and CD control Puneet Gupta*, Andrew B. Kahng*†‡, Chul-Hong Park†, Kambiz Samadi†, and Xu Xu‡ * Blaze-DFM Inc.

Design of Integrated-Circuit Interconnects with Accurate Modeling of Chemical-Mechanical Planarization Lei He, Andrew B. Kahng*, Kingho Tam, Jinjun Xiong.

Statistical Gate Delay Calculation with Crosstalk Alignment Consideration Andrew B. Kahng, Bao Liu, Xu Xu UC San Diego

Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing Puneet Gupta 1 Andrew B. Kahng 1,2,3 O.S. Nakagawa 1 Kambiz.

Design of Integrated-Circuit Interconnects with Accurate Modeling of Chemical-Mechanical Planarization Lei He, Andrew B. Kahng* #, Kingho Tam, Jinjun Xiong.

Methodology from Chaos in IC Implementation Kwangok Jeong * and Andrew B. Kahng *,** * ECE Dept., UC San Diego ** CSE Dept., UC San Diego.

UC San Diego Computer Engineering. VLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD Laboratory.. UC San Diego Computer EngineeringVLSI CAD.

UCSD VLSI CAD Laboratory - ICCAD, Nov. 3, 2009 Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Double Patterning Lithography.

1UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July Is Overlay Error More Important Than Interconnect Variations in Double.

7/14/ Design for Manufacturability Prof. Shiyan Hu Office: EERC 731.

Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning Lithography Kwangok Jeong and Andrew B. Kahng VLSI CAD LABORATORY.

UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD.

UC San Diego / VLSI CAD Laboratory Reliability-Constrained Die Stacking Order in 3DICs Under Manufacturing Variability Tuck-Boon Chan, Andrew B. Kahng,

-1- UC San Diego / VLSI CAD Laboratory Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling Wei-Ting Jonas Chan, Andrew.

A Methodology for Interconnect Dimension Determination By: Jeff Cobb Rajesh Garg Sunil P Khatri Department of Electrical and Computer Engineering, Texas.

Dose Map and Placement Co-Optimization for Timing Yield Enhancement and Leakage Power Reduction Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong.

-1- UC San Diego / VLSI CAD Laboratory A Global-Local Optimization Framework for Simultaneous Multi-Mode Multi-Corner Clock Skew Variation Reduction Kwangsoo.

A New Methodology for Reduced Cost of Resilience Andrew B. Kahng, Seokhyeong Kang and Jiajia Li UC San Diego VLSI CAD Laboratory.

UC San Diego / VLSI CAD Laboratory Toward Quantifying the IC Design Value of Interconnect Technology Improvement Tuck-Boon Chan, Andrew B. Kahng, Jiajia.

-1- UC San Diego / VLSI CAD Laboratory Construction of Realistic Gate Sizing Benchmarks With Known Optimal Solutions Andrew B. Kahng, Seokhyeong Kang VLSI.

Kwangsoo Han, Andrew B. Kahng, Hyein Lee and Lutong Wang

Kwangsoo Han‡, Andrew B. Kahng‡† and Hyein Lee‡

Impact of Interconnect Architecture on VPSAs (Via-Programmed Structured ASICs) Usman Ahmed Guy Lemieux Steve Wilton System-on-Chip Lab University of British.

Process Variation Mohammad Sharifkhani. Reading Textbook, Chapter 6 A paper in the reference.

NUMERICAL TECHNOLOGIES, INC. Assessing Technology tradeoffs for 65nm logic circuits D Pramanik, M Cote, K Beaudette Numerical Technologies Inc Valery Axelrad.

Self-Aligned Double Patterning Decomposition for Overlay Minimization and Hot Spot Detection H. Zhang, Y. Du, M. D.F. Wong, R. Topaloglu Dept. of ECE,

Outline Introduction: BTI Aging and AVS Signoff Problem

Variation. 2 Sources of Variation 1.Process (manufacturing) (physical) variations:  Uncertainty in the parameters of fabricated devices and interconnects.

-1- UC San Diego / VLSI CAD Laboratory Optimization of Overdrive Signoff Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li and Siddhartha Nath Tuck-Boon Chan,

-1- Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products Samyoung Bang #, Kwangsoo Han ‡, Andrew B.

The Interconnect Delay Bottleneck.

Capacitance variation 3/ (%)

Revisiting and Bounding the Benefit From 3D Integration

Double Patterning-Aware Extraction and Static Timing Analysis Flows For Digital Design Sign-Off in 20/14nm Tamer Ragheb, Steven Chan, Adrian Au Yeung,

Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si

Summary Current density in a signal line was estimated, based on the simple circuit shown in Fig.1. This circuit is scaled down according to ITRS 2003.

Is Co-existence Possible?

Presentation transcript:

Assessing Chip-Level Impact of Double Patterning Lithography Kwangok Jeong *, Andrew B. Kahng *,**, and Rasit O. Topaloglu *** * ECE Dept., UC San Diego ** CSE Dept., UC San Diego *** GlobalFoundries, Inc.

(2)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Additional Variability in DPL Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

(3)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Additional Variability in DPL Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

(4)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Double Patterning Lithography (DPL) Pattern-doubling: ‘2X-resolution’ lithography with ‘1X-resolution’ equipment Taxonomy Resist type: positive /negative Methods: double exposure (DE) / double patterning (DP) / spacer double patterning (SDP) Printed feature: line / space Target layer Resist 1 st Exposure 2 nd Exposure Mask1 Mask2 Target layer Resist Mask 1X-resolution 1X 2X-resolution 1X

(5)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Traditional Interconnect Analysis Designers use capacitance tables from foundries 2D/3D field solver with variations  Capacitance tables Major sources of variation: Metal/dielectric density- dependent systematic variation Random process variation Results of variation Width (W) variation Metal height (H) variation Dielectric thickness (D) variation, etc. Traditional interconnect variation analysis 1. for (i = -3 ; i  3 ; i=i+1) { 2. for (j = -3 ; j  3 ; j=j+1) { 3. for (k = -3 ; k  3 ; k=k+1) { 4. W=W nom + i  W  5. H= H nom + j  H  6. D= D nom + k  D  7. run field solver over parameterized structure}}} 8. Find nominal and worst-case capacitance M+1 M-1 M W H D

(6)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Additional Variability in DPL Overlay error Causes: mask misalignment material stress-impacted deformations litho-/etch-impacted topography lens aberration, etc. Impacts on DPL Width variation Space (or pitch) variation  Capacitance variation Alignment metric Indirect: Two DPL masks aligned to a reference layer Error: Direct: Second DPL mask aligned to the first DPL mask Error: S S S S Indirect Alignment (IA) Cc Cg Direct Alignment (DA)

(7)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Additional Variability in DPL Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

(8)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Misalignment in Positive DE/DP WW S S mask2 Positive photoresist Dielectric Space on one side increases Space on the other side decreases Required design of experiments foreach S  (-3  ~ 3  ) mask1  shift by + S/2 mask2  shift by – S/2 end mask1 After exposure + etch Cu filling (misaligned to left)

(9)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Misalignment in Negative DE/DP W’’W’ SS PP S/2 mask1 mask2 (misaligned to left) Negative photoresist Dielectric After exposure + etch After filling Cu Width of one increases Width of the other decreases Required design of experiments foreach S  (-3  ~ 3  ) mask1  change W by + S  shift by S/2 mask2  change W by – S  shift by S/2 end

(10)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Spacer Thickness Variation in Positive SDP Dielectric After exposure + etch (kind of) Positive photoresist Primary patterns Spacers (act as if masks) After filling Cu Cu Width and space change Required design of experiments foreach S  (-3  ~ 3  ) mask1  change W by 0 mask2  change W by + S end WW’’ PP SS

(11)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Spacer Thickness Variation in Negative SDP W’ P’’P’ SS Primary patterns Dielectric After exposure + etch After filling Cu Spacers (act as if masks) (kind of ) Negative photoresist Cu Width and space change Required design of experiments foreach S  (-3  ~ 3  ) mask1  change W by + S/2  shift by + S/4 mask2  change W by + S/2  shift by – S/4 end

(12)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

(13)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 PhotoresistProcessAlignment Experiments: Scenarios We examine impact of misalignment and linewidth variation across various DPL options Parallel 5-Interconnect Structure (TCAD tool) Interconnects in a full-chip (Signoff RCX) Indirect Direct Positive Negative DE DP SDP Direct Positive Negative DE DP SDP

(14)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 TCAD-Based BEOL Analysis Results Capacitance variation due to misalignment in DE/DP IA shows larger variation than DA Negative resist processes have larger variation Capacitance variation in different DPL options SDP has larger variation Negative resist processes have larger variation Capacitance (aF/um)

(15)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Design-Level Analysis - Flow Overlay-aware extraction flow 1. Design GDS TOP.GDS Initial GDS AES core with NanGate 45nm Tech. 2. Split GDS Base GDS Sub-GDS1 Sub-GDS2 DPL layers Non-DPL layers 3. Pattern Decomposition Sub-GDS1-1 Sub-GDS1-2 Sub-GDS2-1 Sub-GDS2-2 ILP-based min cost coloring (Kahng et al. ICCAD08) Coloring and Splitting 4. Shift and Merge (Cadence Virtuoso) Shifting and Merging TOP.GDS 5. Resize and Extraction (Synopsys Hercules, Star-RCXT) Resizing

(16)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Overlay error can cause more than +/- 10% capacitance variation within a die, for all DPL options  Large on-chip variation  Increase of timing optimization difficulty Capacitance Variation (%) Design-Level Capacitance Variation M2 M3 M4M5

(17)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 A net having maximum crosstalk delay (17um long) SDP shows more sensitivity  tighten overlay spec P-DE/DP shows least sensitivity  lessen overlay spec Maximum Crosstalk-Induced Delay P-DE/DP (Space on one side) N-DE/DP (Width) P-SDP (Spaces on both sides) N-SDP (Space & width) M4 |S||S|/2 M2 M4M2 M4 w/o metal fillw/ metal fill

(18)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Total Negative Slack Variation SDP, especially for lower layer (smaller feature), shows more sensitivity  tighter overlay spec TNS Variation (%)

(19)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Outline Double Patterning Lithography (DPL) Traditional Interconnect Analysis Misalignment in Double Patterning Analysis in Different DPL Options Experiments Conclusion

(20)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Summary of Observations Overlay error with indirect alignment (IA) results in higher capacitance variations compared to direct alignment (DA) Capacitance can vary > 10% due to misalignment  Large OCV  increase timing optimization difficulty Timing can be degraded significantly, e.g., > 10% worse TNS P-DE/DP may be the most favorable option for BEOL DPL With the same 3  overlay control, the variation in P-DE/DP is 50% of N-DE/DP or P-SDP, and 25% of N-SDP   Overlay control spec for P-DE/DP can be relaxed by 2X compared to others

(21)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Conclusion and Ongoing Work We provide a variational interconnect analysis framework for double patterning lithography We analyze mechanisms of interconnect variations due to misalignment and spacer thickness variation in DPL We provide both interconnect and design-level RC- extraction framework reflecting interconnect variation in a 45nm DPL process We compare the impact of overlay error in different DPL options Ongoing work Development of timing analysis and optimization methodology considering interconnect variation in DPL Incorporation of statistical techniques to target pessimism reduction

Thank You!

(23)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Impact of Misalignment on FEOL Standard cell decomposition Experimental setup 10nm 3  misalignment is assumed between layers Design of experiments (all permutation: 3*3*3*3 = 81 cases) P1: -10nm (L) / 0nm (C) / +10nm (R) P2: -10nm (L) / 0nm (C) / +10nm (R) M: -10nm (L) / 0nm (C) / +10nm (R) C: -10nm (L) / 0nm (C) / +0nm (R) Original MP1P2C BASE

(24)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Experimental Results on FEOL Flow Impact of misalignment on cell delay is negligibly small (< 2%) Capacitance variation due to misalignment << gate capacitance Measured Delay Variation (%) P1P2M C LCR L L L C R C L C R R L C R C L L C R C L C R R L C R R L L C R C L C R R L C R Tr-level RC-Extraction STAR-RCXT Circuit Simulation HSPICE

(25)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 DPL Options Double ExposureDouble PatterningSpacer-DP Photoresist Printed Feature mask positive resist negative resist After exposure & etch Dielectric After Cu filling (a) Positive-tone(b) Negative-tone Cu interconnect mask positive resist After exposure & etch Dielectric (a) Spaces (Trench-First)(b) Lines Cu interconnect Poly Target layer Resist Hardmask Buffer oxide Hardmask Target layer 1 st Litho-etch Spacer formationOxide depo. CMP Spacer removal 2 nd etch Mask Target layer Resist Hardmask 1 st Litho-etch 2 nd Litho-etch Mask1 Mask2 Target layer Resist 1 st Exposure 2 nd Exposure Mask1 Mask2

(26)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Mask Coloring and Layout Examples in DPL Mechanism of misalignment-induced variation (a) DE and DP Process (b) SDP Process Original patterns Original patterns Coloring Patterns 1 Patterns 2 Coloring Spacer formation (Large spacer) Trim & repair (dark gray) SS Narrow space W W” Dummy for pattern Spacer (gray) a b

(27)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Design-Level Analysis - DOE Design of Experiments for DE/DP with DA 1.foreach layer  { M2, M3, M4, M5 } 2. decompose layer into layer mask1 and layer mask2 3. foreach S  { -3  /2, -2  /2, -  /2, 0,  /2, 2  /2, 3  /2} 4. shift layer mask1 by S 5. shift layer mask2 by –S 6. end 7. layer  layer mask1 + layer mask2 8. foreach  W  { -3  /2, -2  /2, -  /2, 0,  /2, 2  /2, 3  /2} 9. resize layer by  W 10. end 11. merge with other layers 12. RC-Extraction and Timing Analysis 13. end

(28)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Impact on Capacitance Variation Total interconnect capacitance: maximum  C(%) Among top 20% high capacitance nets Impact of overlay < impact of  width Sum of capacitance in the most critical path Critical path has short interconnects  impact of BEOL variation significantly reduces Impact of overlay < impact of  width -3  +3  MinAvgMaxMinAvgMax Overlay-7.7%1.4%9.2%-7.3%1.4%9.7% Width-22.2%4.7%7.1%-3.6%5.3%28.6% Interconnect onlyInterconnect + Gate MinMaxMinMax Overlay-0.08%0.47%-0.04%0.25% Width-1.87%2.59%-0.99%1.38%

(29)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Impact on Crosstalk-Induced Delay Maximum coupling induced delay change PrimeTime-SI (Synopsys) is used to find a net that is mostly affected due to crosstalk Temporal/functional filtering is performed Selected net structure A net with relatively small length (~17um) can have >10%  delay changes due to overlay error Cc (pF)Cg (pF)  Delay Overlay %13.1% Width %15.4% M2 segment: 1.604um M3 segment: 0.78um M4 segment: um Capacitance when  Delay is minimum Capacitance when  Delay is maximum

(30)UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - ISQED 2010, March 23, 2010 Impact on Timing Longest path and total negative slack (TNS) Impact of overlay << impact of  width Longest path delay changes negligibly However, overall timing (TNS) can change significantly Longest path  delay  TNS MinMaxMinMax Overlay-0.06%0.98%3.2%3.8% Width-1.22%2.00%-34.3%49.4% Total Negative Slack (ns)