DDR SDRAM Memory Interface

Quick Start Training Agenda Why DDR? DDR vs. SDR Understanding DDR SDRAM – Bus timing CoolRunner-II and DDR SDRAM demo board CoolRunner-II DDR SDRAM design

Quick Start Training Why DDR? DDR = Double Data Rate Provides ability to read or write two pieces of information in each clock cycle Doubles the bandwidth of the device without increasing the clock speed or bus width

Quick Start Training DDR vs. SDR Functionality Memory core of DDR and SDR are the same – Addressing scheme – Command control interface – Memory bank array structure – Refresh requirements The main difference is in the data interface: – SDR is fully synchronous (posedge of clk) – DDR is true source-synchronous meaning data is captured twice per clock cycle, with a bi-directional data strobe (DQS)

Quick Start Training Strobe-Based Data Bus To allow for higher data rates, data strobe signals were added to DDR devices: – DDR data strobes (DQS) are non-free-running signals that are driven by the device which is driving the data signals Controller drives DQS for WRITE operations DDR SDRAM drives DQS for READ operations

Quick Start Training DDR Enhancements DDR utilizes a differential pair for the system clock (CLK and CLK#) Data is transmitted on both positive and negative edges of the clock DDR devices incorporate an on-chip delay locked loop (DLL) Data strobes are added to improve data capture reliability SSTL_2 signaling techniques are used DDR utilizes a 2n-prefetch architecture – Internal data bus is twice the size of external data bus

Quick Start Training SDR vs. DDR Summary Source- Synchronous SynchronousArchitecture 2x Clock1x ClockData Rate SSTL_2LVTTLSignal Interface 2.5V3.3VV DD and V DD Q YesNoVref YesNoCK# (System Clock) YesNoDQS (Data Strobe) YesNoDM (Data Mask) NoYesDQM DDRSDRParameter

Quick Start Training CoolRunner-II DDR SDRAM Evaluation Board

Quick Start Training CR-II / DDR Demo Board LP V 1.8 V CLK Xilinx CR-II XC2C256 Micron 128 Mb DDR MT46V16M8 Micro Linear ML6554 Bus Terminator V REF Out V TT Out 2.5V/1.8V Regulator V TT & V REF Generation CR-II & DDR SDRAM

Quick Start Training SSTL_2 Termination + - V REF Z O = 50 Ohm RSRS RTRT V TT + - V REF Z O = 50 Ohm RSRS RTRT RSRS RTRT V TT

Quick Start Training CR-II / DDR Termination Z O = 50 Ohm V TT 128 Mb DDR SDRAM V REF

Quick Start Training CPLD Design DDR SDRAM controller design fits into a XC2C256 (~50% utilization for DDR) Includes the following: – Initialization state machine – DDR controller – Refresh logic – Test read/write logic (LFSR) – Board interface

Quick Start Training CPLD Block Diagram DDR Controller State Machine ddr_dq ddr_dqs ddr_cke ddr_clk ddr_clkn ddr_cs ddr_ras ddr_cas ddr_we ddr_a ddr_ba Initialization / Test Logic State Machine int_cmd int_data int_addr Refresh Logic rfsh_flag Board Logic bit LFSR

Quick Start Training DDR Commands

Quick Start Training SDRAM Addressing 23-bit system address bus = 128 MB memory SDRAM data is organized into banks Each bit location is specified with a row and column address Load Mode Register Data Column Address Row Address Bank Address

Quick Start Training Initialization Sequence Wait for stable power & clock inputs NOP Precharge All Addresses Extended Mode Register Write (Enable DLL) Mode Register Write (Reset DLL) Wait 200 Clock Cycles Precharge All Addresses Execute 2 Auto Refresh Commands Mode Register Write (Set CAS & burst)

Quick Start Training Controller State Machine IDLE ACTIVE READ WRITE WR_DATA AUTO_RFS PRECHARGE LOAD_MR CAS_LAT RD_DATA BRST_TERM cnt < BURST_LEN cnt < CAS_LAT cmd = BURST_TERM cmd = PRECHARGE cmd = LOAD MR cmd = READ or WRITE cmd = AUTO_REFRESH

Quick Start Training DDR Clock Requirements

Quick Start Training DDR Clock Generation ddr_clk T Q sys_clk Vcc RST 3.3V IN GCK OBUF 2.5V OUT ddr_clkn T Q Vcc PRE sys_clk 3.3V IN GCK OBUF 2.5V OUT

Quick Start Training DDR Clock Timing 7.5 ns DDR Clock Period 15 ns (133 MHz)(66.67 MHz) sys_clk ddr_clk t CO = 5 ns ddr_clkn T = 7.5 ns T = 15 ns

Quick Start Training DDR Clock Generation (T CO ) ddr_clk sys_clk ddr_clkn

Quick Start Training DDR Clock Generation (V MP ) ddr_clk sys_clk ddr_clkn

Quick Start Training Bank/Row Activation Prior to a READ/WRITE operation the specific bank/row must be activated

Quick Start Training Typical Write Burst DQS generated by CPLD DQS must be center aligned with DQ

Quick Start Training Typical Read Burst DQS is edge aligned to DQ Read interrupted with BURST TERMINATE command

Quick Start Training Data Valid Read Window sys_clk ddr_clk ddr_clkn ddr_dq ddr_dqs DVW D0D0 D1D1 DVW = tCK/2 - tAC(max) + tAC(min) = 7.5 ns - (0.75 ns) + (-0.75 ns) = 6 ns CPLD captures data

Quick Start Training Data Valid Window ddr_dqs ddr_dq(2) ddr_dq(1) ddr_dq(0)

Quick Start Training Read & Write (Burst 2) ddr_clk ddr_dqs ddr_dq(0) ddr_dq(1)

Quick Start Training Read & Write (Burst 4) ddr_dqs ddr_dq(0) ddr_clkn ddr_clk

Quick Start Training Read & Write (Burst 8) ddr_dqs ddr_dq(0) ddr_clkn ddr_clk

Quick Start Training Precharge Operation Precharge deactivates the open row in a particular bank or all banks After a precharge, the specific row address must be activated with an ACTIVE command prior to use Auto PRECHARGE : A10 specifies precharge after current READ/WRITE operation Self PRECHARGE: separate command (must wait t RP )

Quick Start Training Refresh Requirements Refresh is required at intervals of µs – Only one refresh command is required Option to issue up to 8 refresh commands every µs

Quick Start Training DDR SDRAM Vendors Memory vendors providing DDR SDRAM: – Micron, Infineon, Cypress, Samsung, Hitachi, Fujitsu, Hyundai, IDT, Mitsubishi, SiberCore, Toshiba...

Quick Start Training Conclusion Reference board works up to 100 MHz on DDR SDRAM Current DDR design can be modified for SDR SDRAM applications Check out application note XAPP384 on DDR & CoolRunner-II reference design

Demo Slides

Quick Start Training Demo ddr_dq[7:0] 8-bit LFSR Upper Byte Lower Byte int_data[15:0] Burst = 2 Test Control Logic DDR Control Logic 8 8

Quick Start Training Demo Data wrote to DDR Data read from DDR MSB … LSB

Appendix

Quick Start Training SDRAM Core Internal Data Bus DQM (SDR only) Col0 (DDR only)

Quick Start Training SDR Interface

Quick Start Training DDR Interface Col0

Quick Start Training SSTL_2 Signaling

Quick Start Training DDR Write Logic ddr_dq[7:0] ddr_dqs ddr_write_en DualEdge T Q ddr_dqs_t ddr_clk DualEdge T Q int_data (TEST SM Logic) ddr_clk D Q DDR SM Logic ddr_clk 8-bit LFSR D Q lfsr_clk (TEST SM Logic)

Quick Start Training DDR Read Logic ddr_dq[7:0] D Q sys_clk ddr_read_en DualEdge T Q DDR SM Logic ddr_clk CE int_data_rd[15:8] LED Board Logic ddr_dq[7:0] D Q sys_clk CE int_data_rd[7:0] ddr_dqs

Quick Start Training CLK/CLK# Generation