Multi-cycle Implementations Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology January 13, 2012L6-1

Harvard-Style Datapath for MIPS 0x4 RegWrite Add clk WBSrcMemWrite addr wdata rdata Data Memory we RegDst BSrc ExtSelOpCode z OpSel clk zero? clk addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU Control 31 PCSrc br rind jabs pc+4

At least the instruction fetch and a Load (or Store) cannot be executed in the same cycle What problem arises if instructions and data reside in the same memory? Structural hazard

Princeton Microarchitecture Datapath & Control Fetch phase on off = PC

Two-State Controller: Princeton Architecture fetch phase execute phase AddrSrc=ALU IRen=off PCen=on Wen=on AddrSrc=PC IRen=on PCen=off Wen=off A flipflop can be used to remember the phase

Hardwired Controller: Princeton Architecture old combinational logic (Harvard) op code zero? ExtSel, BSrc, OpSel, WBSrc, RegDest, PCsrc1, PCsrc2 MemWrite IR new combinational logic PCen IRen AddrSrc S 1-bit Toggle FF I-fetch / Execute RegWrite Wen

Two-Cycle SMIPS 7 PC Inst Memory Decode Register File Execute Data Memory +4 ir stage January 13, 2012 L6-7http://csg.csail.mit.edu/SNU

Two-Cycle SMIPS module mkProc(Proc); Reg#(Addr) pc <- mkRegU; RFile rf <- mkRFile; Memory mem <- mkMemory; PipeReg#(FBundle) ir <- mkPipeReg; Reg#(Bit#(1)) stage <- mkReg(0); let pcir = ir.first(); let pc = pcir.pc; let inst = pcir.inst; rule doProc; if(stage==0 && ir.notFull) begin //fetch let instResp <- mem(MemReq{op:Ld, addr:pc, data:?}); ir.enq(FBundle{pc:pc, inst:instResp}); stage <= 1; end January 13, 2012 L6-8http://csg.csail.mit.edu/SNU

if(stage==1 && ir.notEmpty) begin //decode let decInst = decode(inst); Data rVal1 = rf.rd1(decInst.rSrc1); Data rVal2 = rf.rd2(decInst.rSrc2); //execute let execInst = exec(decInst, pc, rVal1, rVal2); if(execInst.instType==Ld || execInst.instType==St) execInst.data <- mem(MemReq{op:execInst.instType, addr:execInst.addr, data:execInst.data}); pc <= execInst.brTaken ? execInst.addr : pc+4; //writeback  Two-Cycle SMIPS cont-1 January 13, 2012 L6-9http://csg.csail.mit.edu/SNU

//writeback if(execInst.instType==Alu || execInst.instType==Ld) rf.wr(execInst.rDst, execInst.data); ir.deq; stage <= 0; end endrule endmodule;  Two-Cycle SMIPS cont-2 January 13, 2012 L6-10http://csg.csail.mit.edu/SNU

Processor Performance MicroarchitectureCPIcycle time Microcoded>1short Single-cycle unpipelined1long Pipelined1short Time = Instructions Cycles Time Program Program * Instruction * Cycle –Instructions per program depends on source code, compiler technology and ISA –Cycles per instructions (CPI) depends upon the ISA and the microarchitecture –Time per cycle depends upon the microarchitecture and the base technology

Single-Cycle Hardwired Control: Harvard architecture We will assume clock period is sufficiently long for all of the following steps to be “completed”: 1. instruction fetch 2. decode and register fetch 3. ALU operation 4. data fetch if required 5. register write-back setup time  t C > t IFetch + t RFetch + t ALU + t DMem + t RWB At the rising edge of the following clock, the PC, the register file and the memory are updated

Clock Period t C-Princeton > max {t M, t RF + t ALU + t M + t WB } t C-Princeton > t RF + t ALU + t M + t WB while in the hardwired Harvard architecture t C-Harvard > t M + t RF + t ALU + t M + t WB which will execute instructions faster?

Clock Rate vs CPI Is it possible to design a controller for the Princeton architecture with CPI < 2 ? CPI = Clock cycles Per Instruction Suppose t M >> t RF + t ALU + t WB t C-Princeton = 0.5 * t C-Harvard CPI Princeton = 2 CPI Harvard = 1 No difference in performance!

Princeton microarchitecture (redrawn) The same (mux not shown) Only one of the phases is active in any cycle  a lot of datapath is not in use at any given time fetch phase execute phase addr wdata rdata Memory we ALU Imm Ext PC 0x4 Add IR addr wdata rdata Memory we rd1 GPRs rs1 rs2 ws wd rd2 we

Princeton Microarchitecture Overlapped execution Yes, unless IR contains a Load or Store What do we do with Fetch? fetch phase execute phase addr wdata rdata Memory we ALU Imm Ext PC 0x4 Add IR addr wdata rdata Memory we rd1 GPRs rs1 rs2 ws wd rd2 we How? Can we overlap instruction fetch and execute? ExecuteWhich action should be prioritized? Stall it

Stalling the instruction fetch Princeton Microarchitecture When stall condition is indicated don’t fetch a new instruction and don’t change the PC insert a nop in the IR set the Memory Address mux to ALU (not shown) fetch phase execute phase addr wdata rdata Memory we ALU Imm Ext rd1 GPRs rs1 rs2 ws wd rd2 we PC 0x4 Add addr wdata rdata Memory we stall? nop IR What if IR contains a jump or branch instruction?

Need to stall on branches Princeton Microarchitecture When IR contains a jump or branch-taken no “structural conflict” for the memory but we do not have the correct PC value in the PC memory cannot be used – Address Mux setting is irrelevant insert a nop in the IR insert the nextPC (branch-target) address in the PC addr wdata rdata Memory we ALU Imm Ext rd1 GPRs rs1 rs2 ws wd rd2 we PC 0x4 Add addr wdata rdata Memory we Jump? nop IR

Pipelined Princeton Microarchitecture IR 0x4 clk RegDst PCSrc RegWrite BSrczero? WBSrc 31 ExtSelOpCode Add rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext addr wdata rdata Data Memory z ALU Add OpSel ALU Control clk we MemWrite clk PC PCen MAddrSrc clk nop IRSrc PCSrc2 stall? stall

Pipelined Princeton Architecture Clock:t C-Princeton > t RF + t ALU + t M CPI:(1- f) + 2f cycles per instruction where f is the fraction of instructions that cause a stall What is a likely value of f?