100 Placement Assign logic blocks to specific chip locations Seek to minimize routing distance, congestion CLB IOB.

Slides:



Advertisements
Similar presentations
FPGA-Based System Design: Chapter 4 Copyright  2004 Prentice Hall PTR Topics n Logic synthesis. n Placement and routing.
Advertisements

Simulated Annealing Premchand Akella. Agenda Motivation The algorithm Its applications Examples Conclusion.
ISQED’2015: D. Seemuth, A. Davoodi, K. Morrow 1 Automatic Die Placement and Flexible I/O Assignment in 2.5D IC Design Daniel P. Seemuth Prof. Azadeh Davoodi.
1 Chapter 5 Advanced Search. 2 Chapter 5 Contents l Constraint satisfaction problems l Heuristic repair l The eight queens problem l Combinatorial optimization.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 20: April 13, 2009 Placement II (Simulated Annealing)
Placement 1 Outline Goal What is Placement? Why Placement?
Distance-Vector Routing COS 461: Computer Networks Spring 2010 (MW 3:00-4:20 in COS 105) Michael Freedman
1 Chapter 5 Advanced Search. 2 l
Reconfigurable Computing (EN2911X, Fall07)
Lecture 4: FPGA Placement September 12, 2013 ECE 636 Reconfigurable Computing Lecture 4 FPGA Placement.
Simulated Annealing 10/7/2005.
CS541 Advanced Networking 1 Routing and Shortest Path Algorithms Neil Tang 2/18/2009.
1 Simulated Annealing Terrance O ’ Regan. 2 Outline Motivation The algorithm Its applications Examples Conclusion.
EDA (CS286.5b) Day 7 Placement (Simulated Annealing) Assignment #1 due Friday.
EDA (CS286.5b) Day 19 Covering and Retiming. “Final” Like Assignment #1 –longer –more breadth –focus since assignment #2 –…but ideas are cummulative –open.
Informed Search Chapter 4 Adapted from materials by Tim Finin, Marie desJardins, and Charles R. Dyer CS 63.
Partitioning 1 Outline –What is Partitioning –Partitioning Example –Partitioning Theory –Partitioning Algorithms Goal –Understand partitioning problem.
Routing 2 Outline –Maze Routing –Line Probe Routing –Channel Routing Goal –Understand maze routing –Understand line probe routing.
Lecture 5: FPGA Routing September 17, 2013 ECE 636 Reconfigurable Computing Lecture 5 FPGA Routing.
Partitioning Outline –What is Partitioning –Partitioning Example –Partitioning Theory –Partitioning Algorithms Goal –Understand partitioning problem –Understand.
Introduction to Simulated Annealing 22c:145 Simulated Annealing  Motivated by the physical annealing process  Material is heated and slowly cooled.
ECE 506 Reconfigurable Computing Lecture 7 FPGA Placement.
By Rohit Ray ESE 251.  Most minimization (maximization) strategies work to find the nearest local minimum  Trapped at local minimums (maxima)  Standard.
Introduction to Routing. The Routing Problem Apply after placement Input: –Netlist –Timing budget for, typically, critical nets –Locations of blocks and.
Dijkstra’s Algorithm and Heuristic Graph Search David Johnson.
Placement by Simulated Annealing. Simulated Annealing  Simulates annealing process for placement  Initial placement −Random positions  Perturb by block.
1 IE 607 Heuristic Optimization Simulated Annealing.
Informed Search Chapter 4 (b)
Simulated Annealing.
CALTECH CS137 Fall DeHon 1 CS137: Electronic Design Automation Day 17: November 11, 2005 Placement (Simulated Annealing…)
The Basics and Pseudo Code
CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #14 – Placement.
Modern Floor-planning Based on B ∗ -Tree and Fast Simulated Annealing Paper by Chen T. C. and Cheng Y. W (2006) Presented by Gal Itzhak
CS 484 – Artificial Intelligence1 Announcements Homework 2 due today Lab 1 due Thursday, 9/20 Homework 3 has been posted Autumn – Current Event Tuesday.
1 Chapter 5 Advanced Search. 2 Chapter 5 Contents l Constraint satisfaction problems l Heuristic repair l The eight queens problem l Combinatorial optimization.
1 Simulated Annealing Contents 1. Basic Concepts 2. Algorithm 3. Practical considerations.
Massachusetts Institute of Technology 1 L14 – Physical Design Spring 2007 Ajay Joshi.
Placement. Physical Design Cycle Partitioning Placement/ Floorplanning Placement/ Floorplanning Routing Break the circuit up into smaller segments Place.
Markov Chain Monte Carlo and Gibbs Sampling Vasileios Hatzivassiloglou University of Texas at Dallas.
Modern VLSI Design 3e: Chapter 10 Copyright  1998, 2002 Prentice Hall PTR Topics n CAD systems. n Simulation. n Placement and routing. n Layout analysis.
Thursday, May 9 Heuristic Search: methods for solving difficult optimization problems Handouts: Lecture Notes See the introduction to the paper.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 10: February 6, 2002 Placement (Simulated Annealing…)
Simulated Annealing in 512 bytes EMICRO2004 Microelectronics School Marcelo Johann B R A Z I L.
Simulated Annealing G.Anuradha.
Simulated Annealing. Difficulty in Searching Global Optima starting point descend direction local minima global minima barrier to local search.
Graphs A ‘Graph’ is a diagram that shows how things are connected together. It makes no attempt to draw actual paths or routes and scale is generally inconsequential.
Iterative Improvement Search Including Hill Climbing, Simulated Annealing, WALKsat and more....
FPGA CAD 10-MAR-2003.
Ramakrishna Lecture#2 CAD for VLSI Ramakrishna
An Introduction to Simulated Annealing Kevin Cannons November 24, 2005.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 10: February 16, 2011 Placement II (Simulated Annealing)
Register-Transfer (RT) Synthesis Greg Stitt ECE Department University of Florida.
Intro. ANN & Fuzzy Systems Lecture 37 Genetic and Random Search Algorithms (2)
CS137 Electronic Design Automation Day 9: February 25, 2004 Placement II André DeHon, Michael Wrighton.
Placement and Routing Algorithms. 2 FPGA Placement & Routing.
Scientific Research Group in Egypt (SRGE)
Informed Search Chapter 4 (b)
Partial Reconfigurable Designs
Simulated Annealing Premchand Akella.
Informed Search Chapter 4 (b)
Artificial Intelligence (CS 370D)
CSE 589 Applied Algorithms Spring 1999
Informed Search Chapter 4 (b)
Topics Logic synthesis. Placement and routing..
ESE535: Electronic Design Automation
Xin-She Yang, Nature-Inspired Optimization Algorithms, Elsevier, 2014
ECE 697F Reconfigurable Computing Lecture 4 FPGA Placement
Md. Tanveer Anwar University of Arkansas
A Series of Slides in 5 Parts Movement 4. Best-First
Reconfigurable Computing (EN2911X, Fall07)
Presentation transcript:

100 Placement Assign logic blocks to specific chip locations Seek to minimize routing distance, congestion CLB IOB

101 Placement Cost Function - Wirelength Most systems use Manhattan routing (North, South, East, West, no diagonals) Wirelength estimate = 1/2*(perimeter of bounding box) = “Semi-perimeter” A1A1 A2A2 B1B1 B2B2 B3B3 C1C1 C3C3 C2C2

102 Greedy Placement Create initial placement randomly old_cost = cost(placement); for (iteration = 0; iteration < max_iteration; iteration++) { swap random pair of logic blocks; new_cost = cost(placement); if (old_cost < new_cost) undo_move(); } DA CB

103 Greedy placement algorithms (force-directed, recursive bipartitioning) can easily get stuck in local minima Need a method that is less susceptible to local minima Placement Local Minima d3d3 d4d4 a1a1 a2a2 a3a3 a4a4 b1b1 b2b2 c2c2 c1c1 b4b4 b3b3 d2d2 d1d1 c4c4 c3c3 AB DC DA CB d3d3 d4d4 a1a1 a2a2 c2c2 c1c1 b4b4 b3b3 a3a3 a4a4 b1b1 b2b2 d2d2 d1d1 c4c4 c3c3

104 Annealing Annealing: Cooling hot metals to form good crystal structures Start at high temperatures - atoms move randomly about Cool at specific cooling schedule - leave enough time for atoms to attract into crystal lattice

105 Simulated Annealing Move nodes randomly Initially “high temperature” - allow bad moves to happen Lower temperature, accepting less and less bad moves Slowly “cool” placement to allow good structure to form Possible Placements Cost

106 SA Acceptance Criteria & Cooling Schedule Compute delta = cost(old_placement) - cost(new_placement) if (delta>=0) accept else if ( ) accept, else reject /* 0<=random<=1 */ Initially temperature is very high (most bad moves accepted) Temp slowly goes to 0, with multiple moves attempted at each temperature Final runs with temp=0 (always reject bad moves) greedily “quench” the system

107 SA Cost Function Simulated Annealing requires a cost function that captures quality of placement Smaller cost means better placement Multiple concerns captured in one metric NAND DFF INVNOR

108 Simulated Annealing Algorithm Create initial placement randomly old_cost = cost(placement); for (temp = max_temp; temp >= min_temp; temp = next_temp) { for (iteration = 0; iteration < max_iteration; iteration++) { swap random pair of logic blocks; new_cost = cost(placement); if (old_cost < new_cost) if (random >= Func((old_cost - new_cost)/temperature)) undo_move(); }

109 Routing Assign logic blocks to specific chip locations Seek to minimize routing distance, congestion IOB CLB

110 Route together all the A’s, and all the B’s, minimizing the amount of metal Dark areas are impassible barriers A A A B B A

111 Breadth-first search along “wavefront” Maze Router

112 Cost of each location includes minimum distance to destination Maze Routing Acceleration: A*/Detour Numbers

113 Greedy Multi-terminal Routing Route until first terminal found. Unmark all nodes. Nodes on previous path marked as 1. Continue routing

114 2 Order Independent Routing Can avoid order dependency by iterating: Until good routing found { Route nets independent of congestion Add “penalty” to over-capacity regions } ABCDE WS RQP ONMLKJI HGF VUT