Calibrating Achievable Design Roundtable Discussion June 9, 2002 Facilitator: Bill Joyner, IBM/SRC Wayne Dai, Andrew Kahng, Tsu-Jae King, Wojciech Maly, Igor Markov, Herman Schmit, Dennis Sylvester

2 GSRC Annual Review, Recent Progress in Technology Extrapolation and GTX Transition-aware and active-shielding global signaling approaches, RLC interconnect performance models Transition-aware and active-shielding global signaling approaches, RLC interconnect performance models Taxonomy and correlated models of process variability, and framework for examining impact on achievable design Taxonomy and correlated models of process variability, and framework for examining impact on achievable design New DRAM access time model in support of eDRAM vs. multi-die cost/performance model New DRAM access time model in support of eDRAM vs. multi-die cost/performance model Release of ITRS-2001 ORTCs in GTX Release of ITRS-2001 ORTCs in GTX Updated GTX version in Sematech ITRS-2001 website Updated GTX version in Sematech ITRS-2001 website Enhancements in June02 release Enhancements in June02 release Ongoing studies, modeling of ITRS “shared red bricks” Ongoing studies, modeling of ITRS “shared red bricks” Low-k benefit, variability tolerance of design, design-limiting process rules, … Low-k benefit, variability tolerance of design, design-limiting process rules, …

3 GSRC Annual Review, Recent Progress in CAD-IP Reuse Prototype release of Bookshelf.exe Prototype release of Bookshelf.exe New infrastructure that hosts executable Bookshelf content and allows remote execution New infrastructure that hosts executable Bookshelf content and allows remote execution Web interface, distributed computation platform, and scripting capabilities Web interface, distributed computation platform, and scripting capabilities New tilable (i.e., scalable) circuit benchmarks New tilable (i.e., scalable) circuit benchmarks Network tile Network tile Processing elements (floating-point adder, floating- point multiplier, programmable FIR filter) Processing elements (floating-point adder, floating- point multiplier, programmable FIR filter) Initial discussions of OpenAccess API and data model Initial discussions of OpenAccess API and data model Benchmark scaling approaches Benchmark scaling approaches

4 GSRC Annual Review, Recent Progress in METRICS Expanded METRICS system to front-end acceptance and clock tree synthesis domains Expanded METRICS system to front-end acceptance and clock tree synthesis domains Work with STRJ-WG1 (Japan Roadmap group) to obtain design quality / value survey questions that will be used to survey U.S. companies Work with STRJ-WG1 (Japan Roadmap group) to obtain design quality / value survey questions that will be used to survey U.S. companies Started to propagate open-source METRICS system available to university user group communities Started to propagate open-source METRICS system available to university user group communities Exploring potential links to Bookshelf.exe Exploring potential links to Bookshelf.exe METRICS Birds-of-Feather meeting at DAC-2002 METRICS Birds-of-Feather meeting at DAC-2002 Developing and applying machine learning techniques to improve existing data mining and regression infrastructure Developing and applying machine learning techniques to improve existing data mining and regression infrastructure

5 GSRC Annual Review, Summary: Roles of the C.A.D. Theme u Repository of best known methods, models, metrics s Connects applications and drivers (e.g., ITRS MPU, SOC) to technology roadmap s Connects algorithm (e.g., Fabrics) and design technology (e.g., Power-Energy) within GSRC and to designs, interconnects, devices, and materials (= other FRCs) u Agent of culture change s Measurement & characterization of EDA s Open-source CAD-IP; vertical benchmarking s New vectors: e.g., reusable curriculum IP for VLSI, VLSI design, VLSI design technology education u Identify best opportunities for “sharing of red bricks” between EDA and other semiconductor supplier industries s GTX studies + Manufacturing Calibration: Is low-k worth the development cost? What is the best interconnect process architecture for 65nm? What FEOL and BEOL variabilities can designers tolerate? What is the most cost-effective memory-logic integration? C.A.D. Theme Other FRCs Other GSRC Themes EDA Industry & Academia ITRS Semi Industry Design Houses METRICS & Design Process Opt Models and Calibrations Open-Source CAD-IP Living ITRS What is the design problem? VLSI Design Education Manufacturing Calibration How should Design help solve ITRS red bricks?

6 GSRC Annual Review, C.A.D. Theme Draft Roadmap 1/99 Today 1/03 1/041/05 o Start Fabrics Thrust, initial data model / flow discussions o Fabrics  C.A.D. + Constructive Fabrics Themes o GTX v.1 + ITRS support o METRICS v.1 + start industry integration o 25 slots, first papers 1/01 o GTX v.2 (with ITRS-2001) o GTX model dirs = mfg cost/cal, global sig, mem-logic, app domains o METRICS  broader academic release o BX.exe v.1 Interactions Initiatives and Milestones o ITRS “shared red brick” modeling, analysis, roadmapping o Fabrics Theme – Bookshelf, flows research o ITRS community o Power-Energy Theme – capture/guide o MSD FRC – mfg calibration, manufacturability shared red bricks o Interconnect FRC – model/calib, mfg/var shared red bricks o Self-Test Theme – capture/guide o Vertical benchmarks: cell libraries, DSP, netwk o Open-source RTL-GDSII flow o Natl VLSI design curriculum initiative o NSF (education) o BK 25% PD adopt, 50% slot interop 1/99 Today 1/03 1/041/05 1/01 o Fabrics– “SIP design tech backplane” o NEMI, C2S2 FRC – app roadmaps o “SIP design tech backplane” is METRICized o 30% of ITRS in GTX

7 GSRC Annual Review, Foci of Industry Feedback and Interaction OpenAccess (common data model) – what is GSRC doing? OpenAccess (common data model) – what is GSRC doing? CAD-IP reuse – Bookshelf Slots, codes, functionality CAD-IP reuse – Bookshelf Slots, codes, functionality Benchmarks – “industry-strength validation of research” Benchmarks – “industry-strength validation of research” Education initiative? Education initiative? National-scale VLSI education infrastructure National-scale VLSI education infrastructure ITRS needs (= how to best share “red bricks”) ITRS needs (= how to best share “red bricks”) Incremental benefits of lower k Incremental benefits of lower k “Optimal interconnect stack”? (balancing power delivery, routing density, delay and signal integrity performance, …) “Optimal interconnect stack”? (balancing power delivery, routing density, delay and signal integrity performance, …) “What variability can designers tolerate?” “What variability can designers tolerate?” ESD protection impact on off-chip signaling bandwidth ESD protection impact on off-chip signaling bandwidth Understanding how ground rules impact layout density Understanding how ground rules impact layout density What else? What else?

8 GSRC Annual Review, Roundtable Discussion Questions For our industrial partners: in your designs, what is the largest problem that you face ? For our industrial partners: in your designs, what is the largest problem that you face ? And how does the research work in this Theme help? And how does the research work in this Theme help? What is being done well in this Theme? What is being done well in this Theme? What could be improved? What could be improved? On one or two slides (max), each industrial co-facilitator please summarize key conclusions from this discussion. Questions and issues for discussion not restricted to this set. On one or two slides (max), each industrial co-facilitator please summarize key conclusions from this discussion. Questions and issues for discussion not restricted to this set.