Spin Torque Transfer Logic Proponent; Jim Allen UCSB Friendly Critic: Eli Yablonovitch, Berkeley Reporter: George Bourianoff, Intel.

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Presentation transcript:

Spin Torque Transfer Logic Proponent; Jim Allen UCSB Friendly Critic: Eli Yablonovitch, Berkeley Reporter: George Bourianoff, Intel

Spin Torque Transfer Technology A perspective: from Jim STT-RAM will be developed for memory embedded in logic applications. STT Nano-oscillators development needs to guided by potential application. Research on potential STT Logic will be leveraged by developments in STT-RAM

GMR and STT --- Spin Logic Device? Can we control GMR by Magnetostatically coupling to a STT switch ?? O. Ozatay,a_ N. C. Emley, P. M. Braganca, A. G. F. Garcia, G. D. Fuchs, I. N. Krivorotov,R. A. Buhrman, and D. C. Ralph, “Spin transfer by nonuniform current injection into a nanomagnet”, Appl. Phys. Lett., 88, (2006).

Summary from Eli 1. Giant Magneto-Resistive Effect Switch: Better than today's technology, but not quite to the level of theoretical goal. 2. Spin-Torque Switch: Slightly better than GMR Switch, and capable of achieving theoretical goal at slow clock speeds, <100MHz. Comment - Eli estimates up with 5 μA switching current vs 500 μA experimental

Summary Fig. 13 Current required to observe CIMS as a function of junction size for four different critical current densities. The aspect ratio is assumed to be two. The black thick solid line shows the required current for the magnetic-field write. The gray thick line shows the current that a CMOS with the gate width equal to the junction size can provide (100 μA/100 nm is assumed). The TRS technology nodes are also shown. Symbols are guides for the eyes. Ref 12. Do we know what the critical questions are to make progress? Yes Reduce current for CIMS Demonstration of magneto-static proximity coupling of GMR device and STT switch What are the motivations Non-volatility, low power, integrated logic/memory functionality Can we leverage related technologies? Yes STRAM Does the current status justify more resources? Yes

Other comments Other logic devices are possible e.g. Harris spin FET Latching functionality is very difficult to integrate into clocked, synchronous circuits What is the performance of NAND gate relative to CMOS? Power, speed, area