SENIOR PROJECT By: Ricardo V. Gonzalez Advisor: V. Prasad.

Data Mover Method: in VLSI using LEDIT package Testing being done in LogicWorks and pspice.

OBJECTIVE The main objective is to build a Data Mover with testable features to transfer data from the input to the output in a sequencial manner following an algorithm. This type of design will require the use of CMOS technology and logic gate design to be fabricated into a chip.

TABLE OF CONTENT Block diagram Theory 4-bit data mover (2-bit example) Timing table Controller circuit Complete data mover (two bits example)

TABLE OF CONTENT (CONT..) Trace of data mover Progress up to date Circuitry tested Work left to do Question section

BLOCK DIAGRAM

Theory Following RTL Design Data mover: Memory a[2]; b[2]; c[2] Inputs: x[2] Outputs: z[2] 1 a <= x 2 c <= /a 3 b <= c[0], c[1] 4 c <= a v b 5 z = c

DATA MOVER IN LOGICWORKS

COMPLETE DATA MOVER

VLSI DESIGN OF THE DATA MOVER IN LEDIT

CONTROLLER CIRCUIT IN LEDIT

IDEAL CONTROL TIMING TABLE

TIMING OBTAINED IN SIMULATION

COMPONENTS ALREADY DESIGNED D FLIP-FLOP AND GATE OR GATE SHIFT REGISTER FOR CONTROLLER

D FLIP-FLOP IN LEDIT

D FLIP-FLOP SIMULATION

AND GATE

AND GATE SIMULATION

OR GATE

SIMULATION OF OR GATE

INVERTER GATE

WORK LEFT TO DO FINISH TESTING CONTROLLER CIRCUIT IN LOGICWORKS TEST CONTROLLER CIRCUIT IN LEDIT TEST DATA MOVER FOR PROPER OUTPUTS IN LEDIT OBTAIN DESIGN PAD FOR FINAL PRESENTATION.

THANK YOU QUESTIONS?