Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: 10-20 Ω-cm Thickness: 505-545 µm.

Slides:



Advertisements
Similar presentations
FABRICATION PROCESSES
Advertisements

CMOS Fabrication EMT 251.
Lecture 0: Introduction
Simplified Example of a LOCOS Fabrication Process
CMOS Process at a Glance
VLSI Design Lecture 2: Basic Fabrication Steps and Layout
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.
Introduction to CMOS VLSI Design Lecture 0: Introduction
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
The Physical Structure (NMOS)
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,
Device Fabrication Example
Introduction Integrated circuits: many transistors on one chip.
ECE685 Nanoelectronics – Semiconductor Devices Lecture given by Qiliang Li.
Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.
Katedra Experimentálnej Fyziky Bipolar technology - the size of bipolar transistors must be reduced to meet the high-density requirement Figure illustrates.
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #7. Etching  Introduction  Etching  Wet Etching  Dry Etching  Plasma Etching  Wet vs. Dry Etching  Physical.
Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.
Lithographic Processes
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Fabrication of Active Matrix (STEM) Detectors
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 
Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.
1. A clean single crystal silicon (Si) wafer which is doped n-type (ColumnV elements of the periodic table). MOS devices are typically fabricated on a,
ECE484: Digital VLSI Design Fall 2010 Lecture: IC Manufacturing
SEMINAR PRESENTATION ON IC FABRICATION PROCESS
Virtual NanoFab A Silicon NanoFabrication Trainer
SILICON DETECTORS PART I Characteristics on semiconductors.
Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.
Introduction to Wafer fabrication Process
By: Joaquin Gabriels November 24 th,  Overview of CMOS  CMOS Fabrication Process Overview  CMOS Fabrication Process  Problems with Current CMOS.
NanoFab Trainer Nick Reeder June 28, 2012.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.
Budapest University of Technology and Economics Department of Electron Devices Solution of the 1 st mid-term test 20 October 2009.
IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.
ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.
IC Fabrication/Process
NMOS FABRICATION 1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities.
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
©2008 R. Gupta, UCSD COSMOS Summer 2008 Chips and Chip Making Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.
Fundamentals of Semiconductor Physics 万 歆 Zhejiang Institute of Modern Physics Fall 2006.
Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.
Photo lithography. Why? Add a photo sensitive layer ontop of a material. After treating with UV light, remove the affected areas. After processing (e.g.
CMOS VLSI Fabrication.
CMOS FABRICATION.
Fab - Step 1 Take SOI Wafer Top view Side view Si substrate SiO2 – 2 um Si confidential.
Side ViewTop View Beginning from a silicon wafer.
Patterning - Photolithography
CMOS Fabrication EMT 251.
1. Introduction. Diseño de Circuitos Digitales para Comunicaciones Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration.
Basic Planar Processes
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Fabrication Process terms
Prof. Jang-Ung Park (박장웅)
Manufacturing Process I
Bonding interface characterization devices
1) Wafer Cleaning Oxidizing – Field Oxide
Chapter 1 & Chapter 3.
Fab. Example: Piezoelectric Force Sensor (1)
NanoFab Simulator Update
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
Digital Integrated Circuits A Design Perspective
Silicon Wafer cm (5’’- 8’’) mm
Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si
Manufacturing Process I
Manufacturing Process I
CSE 87 Fall 2007 Chips and Chip Making
1) Wafer Cleaning Oxidizing – Field Oxide (~130 nm)
Presentation transcript:

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm

Oxidize the Si wafer SiO 2

Photo resist Mask A Expose the PR through the mask with UV light Cover the SiO2 with photoresist (PR) Load Mask A

SiO 2 Photo resist Mask A Remove exposed PR Remove SiO 2

::::::::::::: SiO 2 ::::::::::::: Windows Implanted p region B B Remove unexposed PRDoping by ion implantation

:::::::::: SiO 2 :::::::::: Windows Implanted p region B B Remove unexposed PRDoping by ion implantation

::::::::::::: SiO 2 ::::::::::::: B B Al deposition for contacts

::::::::::::: SiO 2 ::::::::::::: B B Lithography (Mask B) Mask B Photo resist

::::::::::::: SiO 2 ::::::::::::: B B Mask B Photo resist Developer/Al Etching

::::::::::::: SiO 2 ::::::::::::: B B Remove unexposed PR p-n junction