Virtex-II Architecture

Virtex-II/Spartan-III 2 Outline CLB Resources Memory and Multipliers I/O Resources Clock Resources

Virtex-II/Spartan-III 3 Virtex-II Architecture I/O Blocks (IOBs) Configurable Logic Blocks (CLBs) Digital Clock Management (DCM) Block SelectRAM Dedicated Multipliers Virtex-II operates at 1.5V

Virtex-II/Spartan-III 4 Distributed SelectRAM : CLB 를 가지고 메모리를 구현함. Block SelectRAM : 메모리 블록을 가지고 메모리를 구현함. Block RAM : Block SelectRAM 과 동일한 의미로 사용이 됨. Block SelectRAM

Virtex-II/Spartan-III 5 CLB Tile CIN Switch Matrix TBUF COUT Slice S0 Slice S1 Fast Connects Slice S2 Slice S3 CIN SHIFT Each CLB contains four slices – Fast Connect provides feedback between slices in the same CLB and routing to neighboring CLBs – A switch matrix provides access to general routing resources

Virtex-II/Spartan-III 6 Outline CLB Resources Memory and Multipliers I/O Resources Clock Resources

Virtex-II/Spartan-III 7 Data Storage Hierarchy Virtex-II supports 3 levels of memory hierarchy On-chip Distributed SelectRAM – Small-to-medium memories – 0.5 ns read access time On-chip Block SelectRAM – Larger memories – True dual-ported operation – 3.3 ns read access time Fast SelectI/O interfaces to external RAM – Fast clock-to-output times enable DLL to boost memory bandwidth

Virtex-II/Spartan-III 8 Block SelectRAM Up to 3.5Mb of RAM in 18kb blocks – Synchronous read and write True dual-port memory – Each port has synchronous read and write capability – Different clocks for each port Synchronous Reset & INIT Values – State machines, decodes, serial to parallel conversion, etc. Supports parity bits – One parity bit per 8 data bits

Virtex-II/Spartan-III 9 Configurations available on each port: True Dual-Port™ Configurations Independent ports A and B configuration: – Support for data width conversion including parity bits Port A: 8-b IN 8-bit OUT 32-bit Port B: 32-b

Virtex-II/Spartan-III 10 Each port supports 3 “ Write Modes ” – Determine how the RAM output behaves during a WRITE operation “ WRITE_FIRST ” mode : Output = New Data – New data is written, and then appears on the RAM output Block SelectRAM Write Modes RAM DO Data_in Data_out = Data_inDI

Virtex-II/Spartan-III 11 Block SelectRAM Write Modes “ READ_FIRST ” mode : Output = Old Data at WRITE address – Previous data value is read from the WRITE address, then held on the output during the WRITE operation RAM DO Data_in DO = prior stored data DI

Virtex-II/Spartan-III 12 Block SelectRAM Write Modes “ NO_CHANGE ” mode : Output = last READ operation – RAM output only changes when WE is inactive RAM DO Data_inDO (no change during Write) DI

Virtex-II/Spartan-III 13 Dedicated Multiplier Blocks 18-bit 2 ’ s complement signed operation Optimized to implement Multiply / Accumulate functions Multipliers are located next to Block SelectRAM 18 x 18 Multiplier Output (36 bits) Data_A (18 bits) Data_B (18 bits)

Virtex-II/Spartan-III 14 Dedicated Multiplier Blocks To create unsigned multipliers, tie the MSBs of inputs A and B to 0 – Up to 17x17 with one multiplier block – Used to create signed multipliers larger than 18x18 To create small signed multipliers, sign extend inputs A and B to the product width – Example, for a 4x4 signed multiplier, sign extend the A and B inputs to 8 bits (tie upper bits to 0)

Virtex-II/Spartan-III 15 XC2V250 Block SelectRAM and Multiplier Locations XC2V3000

Virtex-II/Spartan-III 16 Outline CLB Resources Memory and Multipliers I/O Resources Clock Resources

Virtex-II/Spartan-III 17 IOB Element Reg DDR mux 3-State OCK1 OCK2 Reg DDR mux Output OCK1 OCK2 PAD Reg Input ICK1 ICK2 IOB Input path – Two DDR registers Output path – Two DDR registers – Two 3-state enable DDR registers Separate clocks and clock enables for I and O Set and reset signals are shared

Virtex-II/Spartan-III 18 Double Data Rate Registers Reg DDR mux FDDR OCK1 OCK2 D1 D2 PAD OBUFClock DDR registers can be clocked by – Clock and NOT(Clock) if the duty cycle is 50/50 – The outputs CLK0 and CLK180 of a DCM If D1 = ‘ 1 ’ and D2 = ‘ 0 ’, the output is a copy of Clock – Use this technique to generate a clock output that is synchronized to DDR output data

Virtex-II/Spartan-III 19 Select I/O Select I/O allows connection directly to external signals of varied voltages & thresholds – Processors, memory, bus specific standards, mixed signal... – Provides industry standard IEEE/JDEC I/O standards – Optimizes the speed/noise tradeoff – Saves having to place interface components onto your board I/O pins are divided into 8 “ banks ” – Each bank contains shared Vcco and Vref pins – Only compatible I/O standards can be used within a single bank

Virtex-II/Spartan-III 20 Supported I/O Standards Single-ended I/O standards – LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V) – PCI-X at 133MHz, PCI (3.3V at 33MHz and 66MHz) – GTL, GTLP – HSTL (Class I, II, III, and IV) – SSTL (3.3V and 2.5V, Class I and II) – AGP-2X Differential signaling standards – LVDS, BLVDS, ULVDS – LDT – LVPECL

Virtex-II/Spartan-III 21 DCI provides: – Output drivers that match the impedance of the traces – On-chip termination for receivers and transmitters DCI advantages: – Improves signal integrity by eliminating stub reflections – Reduces board routing complexity and component count by eliminating external resistors – Internal feedback circuit eliminates the effects of temperature, voltage, and process variations Digital Controlled Impedance

Virtex-II/Spartan-III 22 LVDCI and LVDCI_DV2: LVCMOS with adjustable impedance – 3.3V, 2.5V, 1.8V, and 1.5V – Two reference resistors per I/O bank With 1% R, the impedance is within +/- 10% Range:  – LVDCI_DV2: driver impedance is adjusted to half of the reference resistor Controlled Impedance Drivers Vcco GND R R VRN VRP DCI 1 bank DCI...

Virtex-II/Spartan-III 23 On-Chip Termination VCCO Virtex-II VCCO R Z 0 Virtex-II Termination to VCCO (Single Termination) – HSTL Class III & IV – GTL & GTLP – R = 50  Termination to VCCO/2 (Split Termination) – HSTL Class I & II – SSTL 2.5V Class I & II – SSTL 3.3V Class I & II – R = 50  VCCO 2R2R 2R2R Virtex-II VCCO 2R2R 2R2R Z 0 Virtex-II

Virtex-II/Spartan-III 24 Controlled Impedance Drivers with Half Impedance —LVDCI_DV2_15 —LVDCI_DV2_18 —LVDCI_DV2_25 —LVDCI_DV2_33 Single Termination —GTL_DCI —GTLP_DCI —HSTL_III_DCI —HSTL_IV_DCI DCI I/O Standards  Controlled Impedance Drivers —LVDCI_15 —LVDCI_18 —LVDCI_25 —LVDCI_33  Split Termination —HSTL_I_DCI —HSTL_II_DCI —SSTL2_I_DCI* —SSTL2_II_DCI* —SSTL3_I_DCI* —SSTL3_II_DCI* * SSTL compatible

Virtex-II/Spartan-III 25 No more than one DCI I/O standard using Single Termination type is allowed per bank No more than one DCI I/O standard using Split Termination type is allowed per bank Single Termination and Split Termination, Controlled Impedance Driver, and Controlled Impedance Driver with Half Impedance can all co-exist in the same bank – All DCI I/O pins use the same reference resistor value DCI Banking Rules

Virtex-II/Spartan-III 26 Outline  CLB Resources  Memory and Multipliers  I/O Resources  Clock Resources

Virtex-II/Spartan-III 27 Global Clock Routing Resources 16 dedicated Global Clock MUXes / Buffers – 8 on top-center of die, 8 on bottom-center – Can be driven by a clock input pad, a Digital Clock Manager (DCM), or local routing Global Clock MUX provides: – Global Clock Enable capability – Glitch-free switching between clock signals Up to 8 clock nets can be used in each quadrant of the device

Virtex-II/Spartan-III 28 Enhanced Clock Distribution 8 BUFGMUX 16 Clocks SE NE NW SW 8 BUFGMUX NW SW NE SW 16 Clocks 8 BUFGMUX Unused branches are disabled to save power

Virtex-II/Spartan-III 29 Clock Buffer Configurations Clock Buffer (BUFG) – Low skew clock distribution Clock Enable Buffer (BUFGCE) – Holds the clock output low when CE is inactive – CE can be active high or active low – Changes in CE are only recognized when the clock input is low to avoid glitches and short clock pulses OI CE BUFGCE OI BUFG

Virtex-II/Spartan-III 30 Clock Buffer Configurations Clock Multiplexer (BUFGMUX) – Switches glitch-free from one clock to another – After a change on S, the BUFGMUX waits for the currently selected clock input to go low – The output is held low until the newly selected clock goes low, then switches BUFGMUX O I1 I0 S I1 S O Wait for low Switch

Virtex-II/Spartan-III 31 BUFGMUX Sharing 1P1P 1S1S NE SE NW SW 0P0P 0S0S Buffers 0S and 0P compete for quadrant access – A single quadrant cannot access both 0S and 0P Buffers 0S and 1P share common inputs – If 0S is used as a BUFGCE or BUFGMUX, then 1P cannot be used (no inputs left)

Virtex-II/Spartan-III 32 Digital Clock Manager (DCM) Up to 12 DCMs per device – Located on top and bottom edges of the die – Driven by clock input pads DCMs provide: – Delay-Locked Loop (DLL) – Digital Frequency Synthesizer (DFS) – Digital Phase Shifter (DPS) – Digital Spread Spectrum (DSS) Up to 4 outputs of each DCM can drive onto global clock buffers – All DCM outputs can drive general routing

Virtex-II/Spartan-III 33 DLL DFS DPS DCM DSS CLK2X180 CLKFX180 CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV CLKFX CLKIN CLKFB Delay-Locked Loop (DLL) Used to de-skew clocks – Duty cycle correction – Phase shifting – Clock multiplication and division Two frequency modes: – LOW (CLKIN = MHz) – HIGH (CLKIN = MHz) CLK2X, CLK2X180, CLK90, CLK270 outputs not available

Virtex-II/Spartan-III 34 DLL DFS DPS DCM DSS CLK2X180 CLKFX180 CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV CLKFX CLKIN CLKFB Digital Frequency Synthesizer (DFS) CLKFX is any M / D product of CLKIN requency – M = 1 to 4096, D = 1 to 4096 – Default: M=4, D=1 (4X CLKIN) – 50/50 duty-cycle Two frequency modes: – LOW (CLKIN = MHz) CLKFX output must be between MHz – HIGH (CLKIN = MHz) CLKFX output must be between MHz

Virtex-II/Spartan-III 35 Digital Phase Shifter (DPS) Phase shifts all clock outputs by a fraction of CLKIN period – Phase shift remains constant across temperature and voltage Fixed or variable modes – Ports in variable mode (not shown): PSINCDEC input PSEN input PSCLK input PSDONE output – Attribute PHASE_SHIFT = integer (-255 to +255) DLL DFS DPS DCM DSS CLK2X180 CLKFX180 CLK0 CLK90 CLK180 CLK270 CLK2X CLKDV CLKFX CLKIN CLKFB

Virtex-II/Spartan-III 36 Phase Shift Range Phase shift resolution is the greater of: – 1/256 x (CLKIN Period) – 45ps Maximum total phase shift is the smaller of: – One full CLKIN Period – 10ns (in FIXED mode) or 5ns (in VARIABLE mode) Examples: – CLKIN > ~90MHz: minimum step size = 45ps – CLKIN < 100MHz in FIXED mode: maximum shift = 10ns – CLKIN < 200MHz in VARIABLE mode: maximum shift = 5ns

Virtex-II/Spartan-III 37 Phase Shift Effects CLKOUT_PHASE_SHIFT =NONE CLKOUT_PHASE_SHIFT = FIXED CLKIN CLKFB CLKOUT_PHASE_SHIFT =VARIABLE (PS/256) x PERIOD CLKIN (PS negative)(PS positive) CLKIN CLKFB (PS/256) x PERIOD CLKIN (PS negative)(PS positive) CLKIN CLKFB