Silicon Pixel and Strip Detectors for LHC Experiments 1 st Coordination Meeting of the CBM Experiment at the future GSI facility GSI, Nov. 15-16, 2002.

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Presentation transcript:

Silicon Pixel and Strip Detectors for LHC Experiments 1 st Coordination Meeting of the CBM Experiment at the future GSI facility GSI, Nov , 2002 P. Riedler ALICE Silicon Pixel Team CERN

GSI - 15/11/2002P.Riedler - CERN2 Acknowledgements: M. Campbell, P. Collins, H. Dijkstra, F. Faccio, H. Pernegger, G. Stefanini and the ALICE SPD Team

GSI - 15/11/2002P.Riedler - CERN3 GSI - 15/11/2002P.Riedler - CERN3 ALICE Silicon Pixel Telescope Reconstructed event: Testbeam The LHC and its experiments Outline - Radiation damage in silicon - Electronics - Detectors - A closer look at the ALICE SPD

GSI - 15/11/2002P.Riedler - CERN4

GSI - 15/11/2002P.Riedler - CERN5 head-on collisions of protons (7TeV on 7 TeV) and heavy ions L max ~10 34 cm -2 s -1  (4cm)~ (neq) cm -2 in 10 years (>85% charged hadrons) ! RADIATION DAMAGE ! The LHC and its Experiments  Detectors for LHC under full construction now Installation: 2006, First Beam: 2007 => RD groups (e.g. RD48, now RD50) already work on solutions for next generation of detectors

GSI - 15/11/2002P.Riedler - CERN6

GSI - 15/11/2002P.Riedler - CERN7 2 general purpose detectors: Higgs in SM and in MSSM, supersymmetric Particles, B physics (CP violation,...),… ATLAS CMS Strips: 61m 2, 6.3 x 10 6 channels Pixels: ~2m 2, 80 x 10 6 channels 210m 2, 9.6 x 10 6 channels ~2m 2, 33 x 10 6 channels

GSI - 15/11/2002P.Riedler - CERN8 CP violation and rare decaysHeavy ion physics ALICELHCb Strips: 4.9m 2, 2.6 x 10 6 channels Drifts: 1.3m 2, 1.33 x 10 5 channels Pixels: 0.2m 2, 9.83 x 10 6 channels VELO: 0.32m 2, 2 x 10 5 channels Tracker: 14m 2, ~8 x 10 5 channels HPD: ~ 0.02m 2, ~1 x 10 6 channels

GSI - 15/11/2002P.Riedler - CERN9 Silicon Strip Detectors Al strip amplifier SiO 2 /Si 3 N 4 + Vbias n bulk p+p+ n+n+ Each strip is connected to one readout channel N-in-n detectors Double sided detectors Floating intermediate strips … Silicon Pixel Detectors Chip Detector 2-dim matrix of cells Each cell is connected to its own processing electronics high granularity

GSI - 15/11/2002P.Riedler - CERN10 Radiation Damage in Silicon Surface DamageBulk Damage e.g. ATLAS Pixel Detector Electronics Sensitive components are located close to the surface Detectors Full bulk is sensitive to passing charged particles

GSI - 15/11/2002P.Riedler - CERN11 Electronics Cumulative Effects Single Event Effects (SEE) Total Ionizing Dose (TID) Ionisation in the SiO2 and SiO2- Si interface creating fixed charges (all devices can be affected) Displacement Defects (bipolar devices, opto- components) Permanent (e.g. single event gate rupture SEGR) Static (e.g. single event upset SEU) Transient SEEs In the following the effects of TID only will be discussed :

GSI - 15/11/2002P.Riedler - CERN12 Total Ionizing Dose Ionization due to charged hadrons, , electrons,… in the SiO 2 layer and SiO 2 -Si interface Fixed positive oxide charge Accumulation of electrons at the interface Additional interface states are created at the SiO 2 -Si border R. Wunstorf, PhD thesis 1992

GSI - 15/11/2002P.Riedler - CERN13 E.g.: transistor level leakage and threshold voltage shift Parasitic channel between source and drain F. Faccio, ELEC2002 Threshold voltage shift, transconductance and noise degradation, source drain leakage, leakage between devices Effects of TID in CMOS devices

GSI - 15/11/2002P.Riedler - CERN14 Radiation Levels in some LHC experiments total dosefluence 1MeV n eq. [cm -2 ] after 10 years ATLAS Pixels50 Mrad1.5 x ATLAS Strips7.9 Mrad~2 x CMS Pixels~24Mrad~6 x * CMS Strips7.5Mrad1.6 x ALICE Pixel500krad~2 x LHCb VELO- 1.3 x /year** *Set as limit, inner layer reaches this value after ~2 years **inner part of detector (inhomogeneous irradiation ) A radiation tolerant design is important to ensure the functionality of the read out over the full life-time!

GSI - 15/11/2002P.Riedler - CERN15 Solution - Technology Hardening D A C B Flatband-voltage shift as function of the oxide thickness After N.S. Saks, M.G. Ancona, and J.A. Modolo, IEEE Trans.Nucl.Sci., Vol. NS-31 (1984) 1249 Tunneling of trapped charge in thin oxides  V T ~ 1/t ox 2 for t ox > 10nm  V T ~ 1/t ox 3 for t ox < 10nm

GSI - 15/11/2002P.Riedler - CERN16 Using a 0.25µm CMOS process reduces th-shift significantly

GSI - 15/11/2002P.Riedler - CERN17 Enclosed geometrie to avoid leakage Gate SD Standard Geometry Leakage path S D Gate Enclosed Geometry Enclosed gate (S-D leakage) Guard ring (leakage between devices)

GSI - 15/11/2002P.Riedler - CERN18 F. Faccio, ELEC2002

GSI - 15/11/2002P.Riedler - CERN19 Front end technology choices of the different experiments TechnologyChip ALICE Pixel0.25µm CMOSALICE1 ALICE Strips0.25µm CMOSHAL25 ALICE Drift0.25µm CMOSPASCAL ATLAS StripsDMILLABCD ATLAS PixelDMILL->0.25µm CMOSFE-D25 CMS PixelDMILL->0.25µm CMOSPSI CMS Strips0.25µm CMOSAPV25 LHCb VELODMILL/0.25µm CMOSSCTA/Beetle LHCb Tracker0.25µm CMOSBeetle Deep sub-µm means also: speed, low power, low yield, high cost

GSI - 15/11/2002P.Riedler - CERN20 Radiation Damage in Detectors Surface Damage Creation of positive charges in the oxide and additional interface states. Electron accumulation layer. Bulk Damage Displacement of an Si atom and creation of a vacancy and interstitial Point like defects ( , electrons) Cluster Defects (hadrons, ions)

GSI - 15/11/2002P.Riedler - CERN21 Macroscopic Effects Bulk Damage Increase of leakage current Increase of depletion voltage Charge trapping Surface Damage Increase of interstrip capacitance (strips!) Pin-holes (strips!) Effects signal, noise, stability (thermal run-away!) Annealing effects will not be discussed here. But: Do not neglect these effects, esp. for long term running! All experiments have set up annealing scenarios to simulate the damage after 10 years.

GSI - 15/11/2002P.Riedler - CERN22 Leakage current M. Moll - Vertex 2002 Linear increase of leakage current with fluence:  I vol =  ne (  =4-6 x A/cm) But: I prop. Exp(-E g /2kT) Cooling will help! e.g: ATLAS Strips: -7°C CMS Pixel: -8°C P. Riedler Phd-thesis ATLAS Strip detector

GSI - 15/11/2002P.Riedler - CERN23 Depletion Voltage Type-Inversion: n-type bulk starts to behave like p-type bulk -> depletion from the backside of the diode! V dep increases with fluence (after inversion) M. Moll - Vertex 2002 V Before Inversion depletion V After Inversion p+p+ n+n+ If depletion voltage has increased too so much that underdepleted operation is necessary-> charge loss and charge spread!

GSI - 15/11/2002P.Riedler - CERN24 Possible Solutions 1. n-in-n detectors Underdepleted operation is possible! ATLAS pixel CMS pixel LHCb VELO (special case) Fluences close to cm -2 At LHC: Efficiency n-in-np-in-n ATLAS NIM A 450 (2000) 297 ATLAS V bias

GSI - 15/11/2002P.Riedler - CERN25 2. Oxygenated Silicon Defect engineering (RD48) - to reduce reverse annealing => Lower depletion voltage can be expected after several years sunning (including warm-up times) But: improvement only for charged hadrons and . No effect for neutrons observed. Also: spread of depletion voltage of detectors from different suppliers can reduce the beneficial effect ATLAS pixel uses oxygenated Si

GSI - 15/11/2002P.Riedler - CERN26 Further solutions to allow a reasonable operating voltages even after high fluences and annealing: Low resistive silicon Thin detectors (also intersting for material budget reasons) CZ starting material (under investigation) to reduce interstrip capacitance Choice of LHC experiments: ALICEpixelp-in-nstandard FZ ATLAS pixeln-in-noxygenated ATLAS stripsp-in-nstandard FZ CMS pixeln-in-nstandard FZ CMS stripsp-in-nstandard FZ LHCb VELOn-in-nstandard FZ

GSI - 15/11/2002P.Riedler - CERN27 A closer look at the ALICE Silicon Pixel Detector (SPD)  z= 28.3 cm r= 3.9 cm & 7.6 cm 2 barrel layers INFN Padova

GSI - 15/11/2002P.Riedler - CERN28 Sector - Carbon Fibre Support The two barrels will be built of 10 sectors, each equipped with 6 staves: stave INFN Padova Material budget(each layer)≈ 0.9% X 0 (Si ≈ 0.37, cooling ≈ 0.3, bus 0.17, support ≈ 0.1) (lowest material budget of all pixel detectors!)

GSI - 15/11/2002P.Riedler - CERN29 Bus ALICE1LHCb chip Carbon-fibre sector Cooling tube MCM Grounding foil Silicon sensor Each Stave is built of two HALF-STAVES, read out on the two sides of the barrel, respectively. Ladder: 5 chips+1 sensor 193 mm long

GSI - 15/11/2002P.Riedler - CERN30 Bus: 7 layer Al-Kapton flex Wire bonds to the ALICE1LHCb chip 240µm 200µm goal:150µm M.Morel

GSI - 15/11/2002P.Riedler - CERN31 Analog Pilot: Reference bias ADC (T, V and I monitor) Multi Chip Module (MCM) ALICE1LHCb chip Data out Clock JTAG AP DP GOL Digital Pilot: Timing, Control and Readout Laser and pin diode

GSI - 15/11/2002P.Riedler - CERN32 Mixed signal (analogue, digital) Produced in a commercial 0.25µm CMOS process Radiation tolerant design (enclosed gates, guard rings) 8192 pixel cells 50 µm x 425 µm pixel cell ~100 µW/channel ALICE1LHCb chip 13.5 mm 15.8 mm

GSI - 15/11/2002P.Riedler - CERN33 Low minimum threshold: ~1000 electrons Low individual pixel noise:~100 electrons

GSI - 15/11/2002P.Riedler - CERN34 Class I: 42-75% Class II: 6-12% Class III: 17-42% (sample: 4 wafer, 750µm) Production testing will start this autumn Class I - Mean Threshold Fully developed test system for wafers:

GSI - 15/11/2002P.Riedler - CERN35 Ladders and Assemblies Chip Detector Detectors: single chip detectors 5 chip detectors for ladders p-in-n 300 µm thick(tests) - final thickness: 200µm Chips: single chips 750 µm thick (tests) - 150µm final Bump-bonding: VTT/Finland Pb-Sn solder bumps AMS/Italy In bumps

GSI - 15/11/2002P.Riedler - CERN36 chip0chip1chip2chip3chip4 First testbeam with full size ladder - July 2002

GSI - 15/11/2002P.Riedler - CERN37 Detector Chips

GSI - 15/11/2002P.Riedler - CERN38

GSI - 15/11/2002P.Riedler - CERN39 Chip 33Chip 43Chip 50Chip 53Chip 63 Sr-source measurement of thin ladder (300µm chip, 200µm detector) Missing Pixels% missing% working matrices

GSI - 15/11/2002P.Riedler - CERN40 Summary All LHC experiments use silicon detectors to improve their tracking capabilities (up to >200m 2 !). Installation foreseen in The high radiation environment demands radiation tolerant technologies for front end chips and detectors. Almost all silicon detectors use 0.25µm CMOS chips (future?). P-in-n and n-in-n detectors are used depending on the expected fluences and the annealing damage. The current challenges are the actual construction and integration of the detectors.