Turbo decoder Core For ASIC&System Development softDSP Corporation

Turbo code Offers near idealistic, Shannon-limit Error correction performance This great coding capability has lead turbo codes to the standard of 3 rd generation wireless mobile communications (3GPP)

softDSP Turbo decoder Fully Implemented with VHDL and offer flexible interface for use in various applications such as.. 3GPP, Power-line modem, Military comm. Magnetic-storage channel, Satellite comm. High-speed wireless comm. Etc.

Features Use max-log-MAP decoding method as an internal component decoder Use sliding-window technology to reduce memory size 3GPP compliant (block size ) Constraint length K=4, Rate ½, 1/3 5bit input (4-8bit) and internal 8bit processing Easy external I/O interface Easy to modify code to your system

What we offer? (Offering Materials) VHDL Source code Turbo code simulation C-source (floating/fixed point) 3GPP standard interleaver generation C- source (3G TS V.3.2.0) Turbo decoder test vector Designer ’ s guide file

Entire Turbo decoder Core Structure MAP decoder FIFO memory LLR memory Turbo controller SNR scaler Additional circuitry

+ system LLR memory 1 LLR memory 2 MUX Swap Parity alternate First Iter Rd_address Intaddr_require Int_deint Blocksize_2 MAP decoder FIFO logic - MUX parity Interleaver address MUX Int/deint resetstart blocksizeiteration llr_out out_clk Num_iter output_clock rd_clk data_enable SNR scaler Interleaver/Deinterleaver SNR Turbo_ctrl SNR DFF

I/O Interface of Turbo decoder core System Address System Data Parity Address Parity Data Parity Alternate flag Block Size Iteration Number of MAP Iteration Decoded LLR Output Output Enable Output Data Clock Reset CLK Intaddr_require Interleaver_address 13 Start Rd_clk 3 SNR Data Enable Swap Notwr_clk Int_deint Block Size2 13

READ WRITE READ WRITE READ WRITE READ WRITE Decoding Operation Normal vs. Sliding-window (a) Normal Turbo(MAP) decoding operation (b) Sliding-window decoding operation

Procedure of system operation Easy to control : Just by reset and start signal Turbo decoder operates as a slave device of the master processor Turbo decoder generate address signal and get the data and decode it You can extract decoded output just when output clock is validated

Disable Reset signal By asserting start signal, Let the Turbo decoder start decoding Supply System/Parity data and Interleaver address Get the decoded output If decoding of current block ended? The re-assert start signal Operation of external processor Operation of Turbo decoder Initialize Blocksize / Iteration / SNR information Register Memory read address / Interleaver address require signal Get the data & decode it Blocksize, Iteration, SNR

Application system design SoftDSP Turbo decoder core Host processor Start System data memory Parity data memory From equalizer/ RAKE receiver/ AGC etc Reset Interleaver memory Parity_data Parity_address System_data System_address Interleaver_address Intaddr_require Blocksize/Iteration/SNR Int/deint Output data clock Output data Iteration Number Parity_alternate

1-iteration 2-iteration 3-iteration

Overall System specification Critical path: reduce to two 8bit adder (CLA) and two 8bit comparator (Wallace type) including slight counter overhead Gate count: About 24K except memory Performance: shows nice performance over 3dB (Eb/N0)