R. H. Richter et al - VERTEX 2002 Kailua-Kona, DEPFET sensors for a LC vertex detector (1) »DEP(leted)F(ield)E(ffect)T(ransistor) operation principles »Results of pre-tests »DEPFET prototype run »Technology, simulation and design »Wafer thinning »Concept, first results »Summary L. Andricek a, P. Fischer b, K. Heinzinger a, P. Lechner a, G. Lutz a, I. Peric b, M. Reiche c, R.H. Richter a, G. Schaller a, M. Schnecke a, F. Schopper a, H. Soltau a, L. Strüder a, J. Treis a, M. Trimpl b, J. Ulrici b, N. Wermes b a MPI Halbleiterlabor Munich b Univ. of Bonn c MPI für Mikrostrukturphysik Halle, Germany

R. H. Richter et al - VERTEX 2002 Kailua-Kona, DEPFET-Prinziple FET integrated on high ohmic n-bulk Collection of electrons within the internal gate Modulation of the FET current by the signal charge! Radiation ~1  m ~300  m Advantages: Amplification of the charge at the position of collection => no transfer loss Full bulk sensitivity Non structured thin entrance window (backside) Very low input capacitance => very low noise

R. H. Richter et al - VERTEX 2002 Kailua-Kona, ENC = 4.8 +/- 0.1 e K Excellent noise values measured on single pixels

BioScope - imaging of tracer-marked bio-medical samples (P. Klein and W. Neeser) Noise: ca K Slow operation (old technology) Large arrays are impossible (JFET => V P variations) Large cell size

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Rectangular DEPFET pixel detector MOS transistor instead of JFET A pixel size of ca. 20 x 20 µm² is achievable using 3µm minimum feature size.

R. H. Richter et al - VERTEX 2002 Kailua-Kona, DEPFET pixel matrix - Read filled cells of a row - Clear the internal gates of the row - Read empty cells Low power consumption Fast random access to specific array regions

R. H. Richter et al - VERTEX 2002 Kailua-Kona, DEPFET Technology Double poly / double aluminum process on high ohmic n - substrate along p-channel perpendicular to channel (with clear)

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Self aligning Technology Positions of all essential implantations are determined not by masks but by polysilicon layers shallow channel implantation - mandatory for rectangular cells (lateral channel definition) - reduces parameter variations on the wafer

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Technology – pre-tests Motivation oLow leakage current new technology oFirst MOS transistor parameters for the DEPFET and readout electronics design oProcess know how and design rules Pre-tests: Device test: Single poly, single Al, MOS technology on 300µm silicon + Numereous deposition, lithography and etching tests

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Pretest results: Diode leakage currents Reference diodes Pre-test diodes I Bulk =100pA/cm 2

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Linear MOS Transistors (self aligned technolgy) V GS = B =10V L=5µmL=7µm

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Pixel prototype production (6“ wafer) for XEUS and LC (TESLA) Many test arrays - Circular and linear DEPFETS up to 128 x 128 pixels minimum pixel size about 30 x 30 µm² - variety of special test structures Aim: Select design options for an optimized array operation (no charge loss, high gain, low noise, good clear operation) On base of these results => production of full size sensors Production will be finished in spring

purpose detector format pixel size thickness noise readout time / detector / row particle tracking 1.3 x 10 cm² (x 8) 520 x 4000 pixels (x 8) 2.1 Mpix (x8) 25 µm 50 µm ~ 100 el. ENC 50 µsec 20 nsec imaging spectroscopy 7.68 x 7.68 cm² 1024 x 1024 pixels 1 Mpix 75 µm µm 4 el. ENC 1.2 msec 2.5 µsec

Active Pixel Sensor (rectangular) 2 pixels 30 x 30 µm² DEPFET L = 5 µm W = 18 µm  reduce the required read out speed by 2 doubles the number of read out channels

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Potential during collection - 3D Poisson equation (Poseidon) (50µm thick Si, N B =10 13 cm -3,V Back =-20V) Potential during collection - 3D Poisson equation (Poseidon) (50µm thick Si, N B =10 13 cm -3,V Back =-20V) Depth 10µm Depth 7µmDepth 4µmDepth 1µm Sources Drain External (internal) Gates n+ clear contacts Cell size 36 x 27 µm²

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Hiding the n + -clear contacts Depth 1µm The positive Clear pulse removes the electrons from the Internal Gate and also pushs the holes out of the deep p cover region. After returning of the clear the deep p remains negatively charges forming a shield for the signal electrons.

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Potential distribution during Reading Internal Gate Drain Source Back contact 2D dynamic simulation along the channel I D adjusted to 100µA (W/L =18µm/5µm) V internal Gate ca. 3V Localized charge generation simulates a hit

DEPFET simulation – TeSCA (2D, time dependent) hit response to a generation of 1600 electron-hole pairs

TeSCA (2D, time dependent) Removal of 1600 electrons from the internal gate (V Clear =15V) Simulation of the Clear mechanism Poseidon (3D Poisson equ.) Includes 3D effects => V Clear =20V

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Current production status Pixel array section – Design with clockable clear gate N-side view with two polysilicon layers and contact openings To do: - P-side processing - Metallization Drain Gate Clear gate Source 1 Pixel cell

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Processing thin detectors - the Idea -

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Detector thinning – first results Wafer bonding – MPI f. Festkörperstrukturphysik, Halle Wafer grinding – SICO GmbH, Jena Anisotropic etching – CiS gGmbH Erfurt, MPI Halbleiterlabor Munich Thickness of detector region : 50µm of frame : 350µm Size: 8cm x 1cm

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Summary oDEPFET is promising detector candidate for future HE and astrophysics experiments. Key features: low noise, full bulk sensitivity, no charge transfer loss, low power consumption, random access within an array oA new DEPFET technology (2 poly/ 2 aluminum) was developed for large arrays and high speed operation oA DEPFET Prototype production has been started with DEPFET arrays with 30 x 30 µm² pixel size (TESLA) to 75 x 75 µm² XEUS - Technology and device simulations are looking encouraging - Technological pre-tests show very good electrical parameters (leakage currents and MOS transistor characteristics) oA concept for merging the DEPFET technology with a thinning technology is proposed - thin mechanical detector samples were fabricated oFirst wafers will be finished in spring ‘03

R. H. Richter et al - VERTEX 2002 Kailua-Kona, Processing thin detectors - Wafer bonding - 10 “ SOI” Wafer prepared by MPI für Microstrukturphysik, Halle picture from: Q.-Y. Tong and U. Gösele “ Semiconductor Wafer Bonding ” John Wiley & Sons, Inc. ≈1 cm/sec