Efficient Compression and Application of Deterministic Patterns in a Logic BIST Architecture Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin Synopsys Inc. DAC’03 Laboratory of Reliable Computing Department of Electrical Engineering National Tsing Hua University Hsinchu, Taiwan

Chih-Yen Lo 2 Reference  G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A.Hassan, J. Rajski, “Logic BIST for Large Industrial Designs: Real Issues and Case Studies”, International Test Conference1999, pp  H.-J. Wunderlich, G. Kiefer, “Bit-Flipping BIST”, International Conference on Computer-Aided Design,  A. Irion, G. Kiefer, H. Vranken, H.-J. Wunderlich, “Circuit Partitioning for Efficient Logic BIST Synthesis”, Design and Test Europe,  J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thompson, K.H. Tsai, A. Hertwig, N. Tamarapalli. G. Mrugalski, G. Eide, J. Qian, “Embedded Deterministic Test for Low Cost Manufacturing Test”, International Test Conference 2002, pp

Chih-Yen Lo 3 Outline  Introduction  Proposed DBIST solution  Reseeding with 0-cycle overhead  Multiple patterns per seed  Comparing  Results  Conclusions

Chih-Yen Lo 4 Introduction(1/2)  Testing digital circuits represent a big porting of design, manufacture and service cost.  Logic BIST & Scan are used to control test cost.  Logic BIST :  PRPG generate pseudo-random patterns.  Apply them into the internal scan chains of CUT.  Compress the response & Compare it with the signature of the fault-free circuit.  Trade-off between test coverage & test applica- tion time.

Chih-Yen Lo 5 Introduction(2/2)  Several solutions are proposed to address the problem.  Using multiplicity of scan chains  Adding test points to the design  Biasing the pseudo-random patterns  Adding deterministic test patterns  Initialize PRPG to set scan cell to specific values

Chih-Yen Lo 6 Proposed DBIST Solution  DBIST- Combine the same high test coverage as deterministic ATPG with a logic BIST architecture.  DBIST – Deterministic BIST  A modified deterministic ATPG generates the test patterns  Compress them into LFSR seeds.  “care bits” can be set to the desired value, while others are set to pseudo-random values.  Apply them in a modified BIST architecture.

Chih-Yen Lo 7 DBIST Architecture

Chih-Yen Lo 8 DBIST Features  A lot of short parallel scan chains  to reduce test application time  However, its length is no less than shadow chain.  Combinational phase shifter  convert test patterns from 1-D to 2-D  reduce the length of PRPG LFSR  Combinational compactor  compact the results unloaded from scan chains  reduce the length of MISR  PRPG shadow

Chih-Yen Lo 9 PRPG Shadow

Chih-Yen Lo 10 Reseeding with 0-cycle Overhead  No additional cycles are added to reload seed.  No additional cycles are added for the transfer of the new seed to the PRPG LFSR.  No additional cycles are needed to unload PRPG shadow.

Chih-Yen Lo 11 DBIST Self-test  Support special mode to test DBIST logic itself.  PRPG shadow is configured as single scan chain.  PRPG LFSR, MISR and DBIST controller state elements are also configured as scan chains.  All DBIST logic are testable.  DBIST controller  Combinational phase shifter  Combinational compactor  Aforementioned scan chains

Chih-Yen Lo 12 Multiple Patterns per Seed(1/2)  ATPG characteristics:  20 bits scan cells are set for a single fault.  each pattern tests as many faults as possible.  still a small percentage of scan cells are set.  The number of “care bits” per highly compacted pattern drops rapidly.  Maybe thousands of “care bits” at beginning  only be 100 bits after a few hundred patterns  around bits for last hundreds of patterns  In DBIST, the “care bits” are encoded as LFSR seed, while others are generated randomly from the LFSR.

Chih-Yen Lo 13 Multiple Patterns per Seed(2/2)  LFSR spec. chosen by the authors :  The size of LFSR is about bits.  The available “care bits” size is 19 bits less than the length of LFSR.  The test pattern generator must be modified.  A variable-sized set of patterns are encoded into a seed.  If the seed is not exist, remove the “care bits” that target last fault.  cells_per_pattern, total_cells and pats_per_set  Fully utilize the seed size and Reduce total data

Chih-Yen Lo 14 Comparing  Compare DBIST with deterministic patterns  the data reduction  the test cycles reduction  PatsperSeed ~  Clendet/Clenbist ~ 20-30

Chih-Yen Lo 15 Results  The area overhead is 1-2 %  0.2% fault coverage diff. for fault coverage 98% to 99+%  Patdet/Patbist ≥1/2  CPUbist is less than CPUdet.  Data reduction increases with scan cell number.  Cycle reduction is about constant and larger than 10.

Chih-Yen Lo 16 Conclusions  A deterministic BIST method with the same high fault coverage but in a logic BIST architecture.  A variable-size set of test patterns is encoded as a seed.  Seed application is zero-cycle time overhead.  Test data and cycles are both reduced.  All the methods are fully integrated into an automated flow.  design modification  DBIST pattern generation