PLD Technology Basics. Basic PAL Architecture DQ Q CLK OE Fuse.

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Presentation transcript:

PLD Technology Basics

Basic PAL Architecture DQ Q CLK OE Fuse

The type of the configuration cell (Memory) defines the technology Bipolar –metallic fuse, destroyed by prog., One-Time-Programmable (OTP) UV erasable (EPROM) –expensive window package or Plastic OTP, slow erase time Electrical erasable (EEPROM) –multiple read/write cycles, In-System programmable, fast prog and erase, non-volatile CMOS-Memory Cell –volatile, information lost after power-down, reconfigurable, very fast prog. Time, Configuration PROM needed Antifuse, Vialink –open fuse element, programming forms an electrical connection, OTP, long prog times, low impedance interconnect Technology

PAL Architecture Programmable AND Array OR Gates Output Macrocells Dedicated Inputs Clock/Input I/Os PAL SPLDs use a programmable AND array and fixed OR array to create several outputs in a sum-of-products form. SPLDs are commonly referred to as PALs. DQ Q From OR Gate To AND Array Clock I/O These outputs can be either combinatorial or registered in the macrocell.

CPLD Architecture (1) The CPLD is an array of PAL-like devices, interconnected by a switch matrix. Central Switch Matrix PAL Block Dedicated inputs Clock/ Inputs PAL Block I/Os

CPLD Architecture (2)

MACH 4A Device Architecture Clock Generator Logic Array and Allocator Output/ Buried Macrocells Output Switch Matrix I/O Cells Input Switch Matrix PAL Block Central Switch Matrix PAL Block Clock/ Input Pins Dedicated Input Pins I/O Pins Macrocell Feedback I/O Pin Feedback (registered and non-registered)

FPGA Architecture Configurable Logic Block (CLB) Programmable Interconnect Routing I/O Block FPGAs utilize a channeled routing structure to connect blocks of configurable logic

Applications Register Intensive Functions Combinatorial Functions Datapath Functions Register Intensive Narrow Gating Pipelined Systems Dense, Flexible Low Power Lower Speed than CPLDs Control Functions High Speed Wide Gating State Machines Address Decoding Variable Grain Architecture FPGA CPLD

Measurement of Size and Density SPLD –Measured by number of input/outputs (22V10) ASIC –Available gates measured in 2-input equivalents –Usable gates typically 40 to 60 % CPLD –Measured by macrocells ( ) –Typical gate count ranges 1k to 40k FPGA –Measured by gate count (1k to 100k) –Usable gates typically 50 to 60 % Attention! The Art of Gate Counting

In-System Programming Eases Prototyping Easy development Connect cable to PC, programmer or JTAG tester Download software performs the following: Bulk Erases the device (EE only) Serializes the JEDEC (fusemap) file “Bypasses” devices not being programmed Shifts the JEDEC data into the device Programs the JEDEC data into the configuration cells

JTAG-Testing TCK TMS TDI TDO Core Logic Boundary Scan Control Circuit TDI Boundary-Scan Cell (BSC) TDO Core Logic Boundary Scan Control Circuit TMS TCK TMS TDO JTAG-Interface