CTIO Blanco WF Imager Data Acquisition Jon Thaler Fermilab, Dec. 6, 2003

MONSOON Pixel Server MSL (MONSOON Supervisory Level Focus on this connection for a moment Nick Buchholz (12/1/03)

Crude specs Assume: 60 2k  4.6k with 2 amps (E2V) 1 MHz pixel digitization and read rate  Read time is 4.6 s per CCD. 2 bytes per pixel  9  10 9 bits per image Exposure time > 600 sec / 10 (0.5 TB/night) (Mohr/Annis) >120 parallel DAQ channels  dead time below 8%. >Time average data rate (DHE  PAN) ~ 1.2 Mbps/chan  ~150 Mbps total. There is a mismatch between CCD readout and DHE  PAN fiber rate requirements. Monsoon architecture issue?

QuantityItemCost (est.) 1Chassis & Backplane$5k 1 setPower Supplies$1.3k 2 + 1MCB$3.9k 1 + 1CBB$8k 8 + 1IR Acquisition$73.8k 2 + 9Transition Cards$1.6k 2 setsSL100 (DHE & PAN)$10k 1PAN PC$3k Total$107k 2MCB CBB88 1CBB Transition55 8IR Acq IR Acq Transition324 1Power supplies (75% eff.)35 Total dissipated177 NEWFIRM Implementation ( Mark Hunten’s presentation at 12/1/03 Monsoon Status review) Naïve Scaling: Cost~ $200k Power~ 300 W 8 channels each

Space on the Telescope NEWFIRM uses a standard 19” crate We will require two, if this is the route we take. We need to worry about space and power.

Software Pixel Acquisition Node (PAN) SW resides in a PC. Detector Head Electronics (DHE) SW can either be implemented in a processor or as firmware (FPGA). Communications is via Systran fiber optics interfaces. PAN SW (at least for NEWFIRM) has been implemented by the Monsoon group. A DHE SW emulator for the PC has been written by Nick Buchholz (partial implementation?). DHE SW is detector dependent, and wil be a major project.

Pixel Acquisition Node (PAN) Layer No knowledge of other PAN-DHE pairs.No knowledge of other PAN-DHE pairs. Provides PPX interface to MSL or users.Provides PPX interface to MSL or users. Provides run-time configuration of PAN/DHE.Provides run-time configuration of PAN/DHE. Provides first level data archiving.Provides first level data archiving. Provides multiple image processing ‘modes’.Provides multiple image processing ‘modes’. Fowler Sampling, coadds, MSR techniques, OT imaging.Fowler Sampling, coadds, MSR techniques, OT imaging. Provides parameter verification/control/help.Provides parameter verification/control/help. Deals with IR/OUV/etc. differences.Deals with IR/OUV/etc. differences. Handles single exposure sequencing.Handles single exposure sequencing. Handles raw data pre-processing.Handles raw data pre-processing. Provides interface to DHE hardware.Provides interface to DHE hardware. Provides DHE sequencer configuration/download.Provides DHE sequencer configuration/download. Provides PAN error monitoring/reporting/recovery.Provides PAN error monitoring/reporting/recovery. Provides support for ‘speed ROI’.Provides support for ‘speed ROI’. Provides support for ‘compression ROI’s’.Provides support for ‘compression ROI’s’.

Detector Head Electronics (DHE) Layer Handles array hardware control. Voltage levels, sequencing, monitoring.Handles array hardware control. Voltage levels, sequencing, monitoring. Handles integration timing.Handles integration timing. Handles detector readout sequencing.Handles detector readout sequencing. Handles digital averaging.Handles digital averaging. Handles shutter control.Handles shutter control. Can handle array temperature control.Can handle array temperature control. Board Self Identification and Version tracking.Board Self Identification and Version tracking. Some of this is DAQ and some is “front end.”

Near Term Plans Buy a pair of Systran PCI cards to study DHE/PAN communications. Fermilab should probably to the same, so we can coordinate. We must define boundaries and allocate responsibilities. Emulator verification. DHE controller specs? Awaits a sensor decision? Are Systran cards overkill? (e.g., they can do broadcast). How can cost be kept down?