Edge-Triggered D Flip-Flops Discussion D4.2 Example 26.

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Edge-Triggered D Flip-Flops Discussion D4.2 Example 26

Edge-triggered D Flip-flop

-- Example 26: Edge-triggered D flip-flop library IEEE; use IEEE.STD_LOGIC_1164.all; entity flipflop is port( clk : in STD_LOGIC; D : in STD_LOGIC; q : out STD_LOGIC; notq : out STD_LOGIC ); end flipflop; architecture flipflop of flipflop is signal f1,f2,f3,f4,f5,f6: STD_LOGIC; begin f1 <= not(f4 and f2); f2 <= not(f1 and f5); f3 <= not(f6 and f4); f4 <= not(f3 and clk); f5 <= not(f4 and clk and f6); f6 <= not(f5 and D); q <= f1; notq <= f2; end flipflop;

Aldec Active-HDL Simulation

Edge-triggered D Flip-flop with asynchronous set and reset

-- Example 26: ED flip-flop with clr and set library IEEE; use IEEE.STD_LOGIC_1164.all; entity flipflopcs is port( clk : in STD_LOGIC; D : in STD_LOGIC; set : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC; notq : out STD_LOGIC ); end flipflopcs; architecture flipflopcs of flipflopcs is signal f1,f2,f3,f4,f5,f6: STD_LOGIC; begin f1 <= not(f4 and f2 and not set); f2 <= not(f1 and f5 and not clr); f3 <= not(f6 and f4 and not set); f4 <= not(f3 and clk and not clr); f5 <= not(f4 and clk and f6 and not set); f6 <= not(f5 and D and not clr); q <= f1; notq <= f2; end flipflopcs;

Aldec Active-HDL Simulation