S. RossEECS 40 Spring 2003 Lecture 21 CMOS INVERTER CMOS means Complementary MOS: NMOS and PMOS working together in a circuit D S V DD (Logic 1) D S V.

Slides:

Advertisements

Similar presentations

Goals Investigate circuits that bias transistors into different operating regions. Two Supplies Biasing Four Resistor Biasing Two Resistor Biasing Biasing.

Advertisements

Physical structure of a n-channel device:

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

DC Characteristics of a CMOS Inverter

ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Lecture 28 Field-Effect Transistors.

DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter

Lecture 5: DC & Transient Response

(Neil weste p: ).  A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain.

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004.

CURRENT MIRROR/SOURCE EMT451/4. DEFINITION Circuit that sources/sinks a constant current as biasing elements as load devices for amplifier stages.

VLSI Design CMOS Transistor Theory. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V.

S. RossEECS 40 Spring 2003 Lecture 22 Inside the CMOS inverter, no I D current flows through transistors when input is logic 1 or logic 0, because the.

S. RossEECS 40 Spring 2003 Lecture 27 Today we will Put a twist on our normally linear operational amplifier circuits to make them perform nonlinear computations.

DC Characteristics of a CMOS Inverter A complementary CMOS inverter consists of a p-type and an n-type device connected in series. The DC transfer characteristics.

Lecture #26 Gate delays, MOS logic

10/8/2004EE 42 fall 2004 lecture 171 Lecture #17 MOS transistors MIDTERM coming up a week from Monday (October 18 th ) Next Week: Review, examples, circuits.

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response

S. RossEECS 40 Spring 2003 Lecture 20 Today we will Review NMOS and PMOS I-V characteristic Practice useful method for solving transistor circuits Build.

EXAMPLES OF FEEDBACK Today we will

11/5/2004EE 42 fall 2004 lecture 281 Lecture #28 PMOS LAST TIME: NMOS Electrical Model – NMOS physical structure: W and L and d ox, TODAY: PMOS –Physical.

Week 9b, Slide 1EECS42, Spring 2005Prof. White Week 9b OUTLINE Digital logic functions NMOS logic gates The CMOS inverter Reading Rabaey et al.: Section.

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture.

Lecture 21 Today we will Revisit the CMOS inverter, concentrating on logic 0 and logic 1 inputs Come up with an easy model for MOS transistors involved.

Lecture 17 Today we will discuss

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory

(N-Channel Metal Oxide Semiconductor)

The metal-oxide field-effect transistor (MOSFET)

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004 from CMOS VLSI Design A Circuits and Systems.

Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley.

11/3/2004EE 42 fall 2004 lecture 271 Lecture #27 MOS LAST TIME: NMOS Electrical Model – Describing the I-V Characteristics – Evaluating the effective resistance.

DC and transient responses Lezione 3

S. Reda VLSI Design Design and Implementation of VLSI Systems (EN1600) lecture09 Prof. Sherief Reda Division of Engineering, Brown University Spring 2008.

CMOS VLSI Design4: DC and Transient ResponseSlide 1 EE466: VLSI Design Lecture 05: DC and transient response – CMOS Inverters.

Chap. 5 Field-effect transistors (FET) Importance for LSI/VLSI –Low fabrication cost –Small size –Low power consumption Applications –Microprocessors –Memories.

EE4800 CMOS Digital IC Design & Analysis

© Electronics Recall Last Lecture The MOSFET has only one current, I D Operation of MOSFET – NMOS and PMOS – For NMOS, V GS > V TN V DS sat = V GS – V.

Lecture 2: CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response Greco/Cin-UFPE (Material taken/adapted from Harris’ lecture notes)

EE 447 VLSI Design 4: DC and Transient Response1 VLSI Design DC & Transient Response.

VLSI design Lecture 1: MOS Transistor Theory. CMOS VLSI Design3: CMOS Transistor TheorySlide 2 Outline  Introduction  MOS Capacitor  nMOS I-V Characteristics.

12/10/2004EE 42 fall 2004 lecture 421 Lecture #42: Transistors, digital This week we will be reviewing the material learned during the course Today: review.

S. RossEECS 40 Spring 2003 Lecture 24 Today we will Review charging of output capacitance (origin of gate delay) Calculate output capacitance Discuss fan-out.

Slide 1EE40 Fall 2009Prof. Cheung EE40 Final Exam Review Prof. Nathan Cheung 12/01/2009 Practice with past exams

Transistor Characteristics EMT 251. Outline Introduction MOS Capacitor nMOS I-V Characteristics (ideal) pMOS I-V Characteristics (ideal)

Lecture 3: CMOS Transistor Theory

Transistors Three-terminal devices with three doped silicon regions and two P-N junctions versus a diode with two doped regions and one P-N junction Two.

ECE 342 Electronic Circuits 2. MOS Transistors

Mary Jane Irwin ( ) Modified by Dr. George Engel (SIUE)

Mary Jane Irwin ( ) CSE477 VLSI Digital Circuits Fall 2002 Lecture 04: CMOS Inverter (static view) Mary Jane.

Ch 10 MOSFETs and MOS Digital Circuits

Electronic Circuits Laboratory EE462G Lab #7 NMOS and CMOS Logic Circuits.

ECE 340 ELECTRONICS I MOS APPLICATIONS AND BIASING.

Device Characterization ECE/ChE 4752: Microelectronics Processing Laboratory Gary S. May April 1, 2004.

1 Fundamentals of Microelectronics  CH1 Why Microelectronics?  CH2 Basic Physics of Semiconductors  CH3 Diode Circuits  CH4 Physics of Bipolar Transistors.

Introduction to CMOS VLSI Design MOS devices: static and dynamic behavior.

1 Chapter 5. Metal Oxide Silicon Field-Effect Transistors (MOSFETs)

EE210 Digital Electronics Class Lecture 7 May 22, 2008.

Electronic Circuits Laboratory EE462G Lab #7 NMOS and CMOS Logic Circuits.

11. 9/15 2 Figure A 2 M+N -bit memory chip organized as an array of 2 M rows  2 N columns. Memory SRAM organization organized as an array of 2.

MOSFET DC circuit analysis Common-Source Circuit

Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2007.

1 Tai-Cheng Lee Spring 2006 MOS Field-Effect Transistors (MOS) Tai-Cheng Lee Electrical Engineering/GIEE, NTU.

Lecture 20 Today we will Look at why our NMOS and PMOS inverters might not be the best inverter designs Introduce the CMOS inverter Analyze how the CMOS.

Solid-State Devices & Circuits

CMOS Logic Gates. NMOS transistor acts as a switch 2 When gate voltage is 0 V No channel is formed current does not flow easily “open switch” When gate.

Recall Lecture 17 MOSFET DC Analysis 1.Using GS (SG) Loop to calculate V GS Remember that there is NO gate current! 2.Assume in saturation Calculate I.

Introduction to CMOS VLSI Design CMOS Transistor Theory

ECE 333 Linear Electronics

Wujie Wen, Assistant Professor Department of ECE

Presentation transcript:

S. RossEECS 40 Spring 2003 Lecture 21 CMOS INVERTER CMOS means Complementary MOS: NMOS and PMOS working together in a circuit D S V DD (Logic 1) D S V OUT V IN

S. RossEECS 40 Spring 2003 Lecture 21 V OUT V IN CB A E D V DD V M : Voltage when V IN = V OUT (= V M ) CMOS INVERTER RESPONSE

S. RossEECS 40 Spring 2003 Lecture 21 triode mode saturation mode V DS IDID V GS = 3 V V GS = 1 V V DS = V GS - V TH(N) LAST TIME: SINGLE TRANSISTOR CIRCUIT Linear I D vs V DS given by surrounding circuit X X

S. RossEECS 40 Spring 2003 Lecture 21 ANALYSIS OF INVERTER CIRCUT Obtain: 1)the two nonlinear I D vs. V DS equations for the transistors: I D(N) vs. V DS(N) and I D(P) vs. V DS(P) 2)A linear relationship between I D(N) and I D(P) (e.g., via KCL) 3)An independent linear relationship between V DS(N) and V DS(P) (e.g. via KVL) Using the above, write: I D(P) vs. V DS(P) in terms of I D(N) vs. V DS(N) (or vice-versa) Solve the two transistor equations simultaneously.

S. RossEECS 40 Spring 2003 Lecture 21 ANALYSIS OF INVERTER CIRCUIT: UNLOADED D S V DD (Logic 1) D S V OUT V IN 1)Transistor equations: I D(N) = f N (V DS(N) ) I D(P) = f P (V DS(P) ) 2)I D(P) +I D(N) = 0 3)V DS(N) -V DS(P) = V DD Rewrite 1) as I D(N) = -f P (V DS(N) -V DD ) Find simultaneous solution to: I D(N) = f N (V DS(N) ) I D(N) = -f P (V DS(N) -V DD )

S. RossEECS 40 Spring 2003 Lecture 21 D S V DD (Logic 1) D S V OUT V IN ANALYSIS OF INVERTER CIRCUIT: UNLOADED Also note: V GS(N) = V IN V GS(P) = V IN - V DD V OUT = V DS(N) + V GS(N) - + V GS(P) - + V DS(N) _

S. RossEECS 40 Spring 2003 Lecture 21 V DS IDID V GS(P) < V TH(N) - V DD V GS(N) < V TH(N) CMOS INVERTER: REGION A V DS(P) = V GS(P) - V TH(P) NMOS cutoff mode PMOS triode mode V DD No current flow in Region A!

S. RossEECS 40 Spring 2003 Lecture 21 V DS IDID V GS(P) = V TH(N) +  - V DD V GS(N) = V TH(N) +  V DS(N) = V GS(N) - V TH(N) CMOS INVERTER: REGION B V DS(P) = V GS(P) - V TH(P) NMOS saturation mode PMOS triode mode V DD

S. RossEECS 40 Spring 2003 Lecture 21 V DS IDID V DS(N) = V GS(N) - V TH(N) CMOS INVERTER: REGION C V DS(P) = V GS(P) - V TH(P) NMOS saturation mode PMOS saturation mode V DD

S. RossEECS 40 Spring 2003 Lecture 21 V DS IDID V GS(P) = V TH(P) -  V GS(N) = V DD + V TH(P) -  V DS(N) = V GS(N) - V TH(N) CMOS INVERTER: REGION D V DS(P) = V GS(P) - V TH(P) NMOS triode mode PMOS saturation mode V DD

S. RossEECS 40 Spring 2003 Lecture 21 V DS IDID V GS(P) > V TH(P) V GS(N) > V TH(P) + V DD CMOS INVERTER: REGION E V DS(N) = V GS(N) - V TH(N) NMOS triode mode PMOS cutoff mode V DD No current flow in Region E!

S. RossEECS 40 Spring 2003 Lecture 21 IDID V IN CB A E D V DD CMOS INVERTER RESPONSE: CURRENT FLOW

S. RossEECS 40 Spring 2003 Lecture 21 No I D current flow in Regions A and E if nothing attached to output; current flows only during logic transition If resistor or diode attached to output, current will flow through PMOS when input is low (output is high) If another inverter (or other CMOS logic) attached to output, transistor gate terminals of attached stage do not permit current: current flows only during logic transition D S V DD D S V OUT1 V IN D S V DD D S V OUT2

S. RossEECS 40 Spring 2003 Lecture 21 EXAMPLE: RESISTIVE LOAD D S V DD = 5 V D S V OUT 1)Transistor equations: I D(N) = 0 A (NMOS cutoff) V IN = 0 V Find the power absorbed by the resistor and the inverter. Power absorbed by inverter: P = I D(P) V DS(P) + I D(N) V DS(N) Let W/L  C OX = 1 mA, V TH(N) = -V TH(P) = 1 V, = 0. 1 k 

S. RossEECS 40 Spring 2003 Lecture 21 EXAMPLE: RESISTIVE LOAD D S V DD = 5 V D S V OUT 2)I D(N) and I D(P) relationship: I D(P) +I D(N) = -V OUT / 1 k  3)V DS(N) and V DS(P) relationship: V DS(N) -V DS(P) = V DD V IN = 0 V 1 k  4) Substitute into PMOS transistor equation:

S. RossEECS 40 Spring 2003 Lecture 21 EXAMPLE: RESISTIVE LOAD D S V DD = 5 V D S V OUT V IN = 0 V 1 k  5)Solutions: V DS(P) = {-8.87 V, V} V DS(P) = V agrees with triode mode I D(P) = mA Power absorbed by inverter: I D(P) V DS(P) + I D(N) V DS(N) = 3.66 mW Power absorbed by resistor: R I 2 = (1 k  )(-3.24 mA) 2 = 10.5 mW