Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program Tezaswi Raja Vishwani Agrawal Michael L. Bushnell Rutgers University, Dept. of ECE Piscataway, NJ Support from National Science Foundation, USA

January 2003VLSI Design Conf.2 Power in a CMOS Gate VDD = 5V IDD Ground

January 2003VLSI Design Conf.3 Problem Statement Design a digital circuit for minimum transient energy consumption by eliminating hazards

January 2003VLSI Design Conf.4 Theorem 1 For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition Ref: Agrawal, et al., VLSI Design’99

January 2003VLSI Design Conf.5 Given that events occur at the input of a gate (inertial delay = d ) at times t 1 <... < t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t d t n - t 1 + d t n - t 1 + d t 1 t 2 t 3 t n t n + d t 1 t 2 t 3 t n t n + d time time Ref: Agrawal, et al., VLSI Design’99

January 2003VLSI Design Conf.6 Minimum Transient Design Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

January 2003VLSI Design Conf.7 Linear Program (LP) Variables: gate and buffer delays Objective: minimize number of buffers Subject to: overall circuit delay Subject to: minimum transient condition for multi-input gates AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)

January 2003VLSI Design Conf.8 Limitations of This LP Constraints are written by path enumeration. Since number of paths in a circuit can be exponential in circuit size, the formulation is infeasible for large circuits. Example: c880 has 6.96M constraints.

January 2003VLSI Design Conf.9 A New LP Model Introduce two new timing window variables per gate output: t i Earliest time of signal transition at gate i. T i Latest time of signal transition at gate i. t 1, T 1 t n, T n t i, T i Ref: T. Raja, Master’s Thesis, Rutgers Univ., 2002

January 2003VLSI Design Conf.10 New Linear Program Gate variables d 4... d 12 Buffer Variables d d 29 Corresponding window variables t 4... t 29 and T 4... T 29.

January 2003VLSI Design Conf.11 Multiple-Input Gate Constraints For Gate 7: T 7 > T 5 + d 7 ; t 7 T 7 - t 7 ; T 7 > T 6 + d 7 ; t 7 < t 6 + d 7 ;

January 2003VLSI Design Conf.12 Single-Input Gate Constraints T 16 + d 19 = T 19 ; t 16 + d 19 = t 19 ; Buffer 19:

January 2003VLSI Design Conf.13 Overall Delay Constraints T 11 < maxdelay T 12 < maxdelay

January 2003VLSI Design Conf.14 Why New Model is Superior? Path constraints from old model: 2 × 2 × … 2 = 2 n paths between I/O pair For new model, a single constraint controls I/O delay. Total variables, 24n. New constraint set is linear in size of circuit.

January 2003VLSI Design Conf.15 Comparison of Constraints Number of gates in circuit Number of constraints 6.96M 3,611 c880

January 2003VLSI Design Conf.16 Results: 1-Bit Adder

January 2003VLSI Design Conf.17 Estimation of Power Circuit is simulated by an event-driven simulator for both optimized and un- optimized gate delays. All transitions at a gate are counted as Events[gate]. Power consumed  Events[gate] x # of fanouts. Ref: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ICCAD`97).

January 2003VLSI Design Conf.18 Original 1-Bit Adder Color codes for number of transitions

January 2003VLSI Design Conf.19 Optimized 1-Bit Adder Color codes for number of transitions

January 2003VLSI Design Conf.20 Results: 1-Bit Adder Simulated over all possible vector transitions Average power = optimized/unit delay = 244 / 308 = Peak power = optimized/unit delay = 6 / 10 = 0.60 Power Savings : Peak = 40 % Average = 21 %

January 2003VLSI Design Conf.21 Results: 4-Bit ALU maxdelayBuffers inserted Power Savings : Peak = 33 %, Average = 21 %

January 2003VLSI Design Conf.22 Benchmark Circuits Circuit C432 C880 C6288 c7552 Maxdel. (gates) No. of Buffers Average Peak Normalized Power

January 2003VLSI Design Conf.23 Physical Design Gate l/w Gate l/w Gate l/w Gate l/w Gate delay modeled as a linear function of gate size, total load capacitance, and fanout gate sizes (Berkelaar and Jacobs, 1996). Layout circuit with some nominal gate sizes. Enter extracted routing delays in LP as constants and solve for gate delays. Change gate sizes as determined from a linear system of equations. Iterate if routing delays change.

January 2003VLSI Design Conf.24 Power Dissipation of ALU4

January 2003VLSI Design Conf.25 References R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10 th Int’l Conf. VLSI Design, Jan. 1997, pp V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12 th Int’l Conf. VLSI Design, Jan. 1999, pp M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp T. Raja, A Reduced Constraint Set Linear Program for Low Power Design of Digital Circuits, Master’s Thesis, Rutgers Univ., New Jersey, 2002.

January 2003VLSI Design Conf.26 Conclusion Obtained an LP constraint-set that is linear in the size of the circuit. LP solution: Eliminates glitches at all gate outputs, Holds I/O delay within specification, and Combines path-balancing and hazard-filtering to minimize the number of delay buffers. New LP produces results exactly identical to old LP requiring exponential constraint-set. Results show peak power savings up to 68% and average power savings up to 64%.