Fall 06, Sep 19, 21 ELEC / Lecture 6 1 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL

Fall 06, Sep 19, 21ELEC / Lecture 62 CMOS Dynamic Power Dynamic Power = Σ0.5 α i f clk C Li V DD 2 All gates i ≈ 0.5 α f clk C L V DD 2 ≈ α 01 f clk C L V DD 2 whereαaverage gate activity factor α 01 = 0.5α, average 0→1 trans. f clk clock frequency C L total load capacitance V DD supply voltage

Fall 06, Sep 19, 21ELEC / Lecture 63 Example: 0.25μm CMOS Chip f = 500MHz f = 500MHz Average capacitance = 15 fF/gate Average capacitance = 15 fF/gate V DD = 2.5V V DD = 2.5V 10 6 gates 10 6 gates Power= α 01 f C L V DD 2 Power= α 01 f C L V DD 2 = α 01 ×500×10 6 ×(15× ×10 6 ) ×2.5 2 = 46.9W, for α 01 = 1.0

Fall 06, Sep 19, 21ELEC / Lecture 64 Signal Activity, α T=1/f Clock α 01 = 1.0 α 01 = 0.5 Comb. signals

Fall 06, Sep 19, 21ELEC / Lecture 65 Reducing Dynamic Power Dynamic power reduction is Dynamic power reduction is Quadratic with reduction of supply voltage Quadratic with reduction of supply voltage Linear with reduction of capacitance Linear with reduction of capacitance

Fall 06, Sep 19, 21ELEC / Lecture μm CMOS Inverter, V DD =2.5V V in (V) V out (V) V in (V) Gain = dV out /dV in

Fall 06, Sep 19, 21ELEC / Lecture μm CMOS Inverter, V DD < 2.5V V in (V) V out (V) V in (V) V out (V) Gain = -1 V th = 0.4 V Similar to analog amplifier

Fall 06, Sep 19, 21ELEC / Lecture 68 Low Voltage Operation (V DD > V th ) Reduced dissipation, increased delay. Reduced dissipation, increased delay. Operation sensitive to variations in device parameters like V th. Operation sensitive to variations in device parameters like V th. Reduced signal swing reduces internal noise (crosstalk), increases sensitivity to external noise. Reduced signal swing reduces internal noise (crosstalk), increases sensitivity to external noise.

Fall 06, Sep 19, 21ELEC / Lecture 69 Impact of V DD on Performance C L V DD Inverter delay = K───────, Power ~ C L V DD 2 (V DD – V th ) α 0.4V 1.45V2.5V V DD Power Delay Delay (ns) V DD =V th

Fall 06, Sep 19, 21ELEC / Lecture 610 Optimum Power × Delay V DD 3 Power × Delay, PD=constant ×─────── (V DD – V th ) α For minimum power-delay product, d(PD)/dV DD = 0 (V DD – V th ) α 3V DD 2 – V DD 3 α (V DD – V th ) α – 1 ———————————————————— = 0 (V DD – V th ) 2α 3V DD – 3V th = α V DD V DD =3 V th / (3 – α)

Fall 06, Sep 19, 21ELEC / Lecture 611 Optimum Power × Delay (Cont.) For minimum power-delay product, d(PD)/dV DD = 0 3V th V DD =─── 3 – α For long channel devices, α = 2, V DD = 3V th For very short channel devices, α = 1, V DD = 1.5V th

Fall 06, Sep 19, 21ELEC / Lecture 612 Very Low Voltage Operation V DD < V th V DD < V th Operation via subthreshold current. Operation via subthreshold current. Small currents have long charging and discharging times – very slow speed. Small currents have long charging and discharging times – very slow speed. Increasing sensitivity to thermal noise. Increasing sensitivity to thermal noise.

Fall 06, Sep 19, 21ELEC / Lecture 613 Lower Bound on V DD For proper operation of gate, maximum gain (for Vin = V DD /2) should be greater than 1. For proper operation of gate, maximum gain (for Vin = V DD /2) should be greater than 1. Gain = - (1/n)[exp(V DD / 2Φ T ) – 1] = - 1 Gain = - (1/n)[exp(V DD / 2Φ T ) – 1] = - 1 n = 1.5 n = 1.5 Φ T = kT/q = 25 mV at room temperature Φ T = kT/q = 25 mV at room temperature V DD = 48 mV V DD = 48 mV V DDmin > 2 to 4 times kT/q or ~ 50 to 100 mV at room temperature (27 o C) V DDmin > 2 to 4 times kT/q or ~ 50 to 100 mV at room temperature (27 o C) Ref.: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, A Design Perspective, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, Chapter 5. Ref.: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, A Design Perspective, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, Chapter 5.

Fall 06, Sep 19, 21ELEC / Lecture 614 Capacitance Reduction Transistor sizing for Transistor sizing for Performance Performance Power Power

Fall 06, Sep 19, 21ELEC / Lecture 615 Basics of Sizing (S = Scale Factor) Sizing a gate by factor S means all transistors in that gate have their widths W changed to WS. Lengths (L) of transistors is left unchanged. Sizing a gate by factor S means all transistors in that gate have their widths W changed to WS. Lengths (L) of transistors is left unchanged. On resistance of the scaled transistor is reduced as 1/S On resistance of the scaled transistor is reduced as 1/S Gate capacitance is scaled as S Gate capacitance is scaled as S Next we consider the delay and power of the original and scaled gates. Next we consider the delay and power of the original and scaled gates.

Fall 06, Sep 19, 21ELEC / Lecture 616 A Standard Inverter, S = 1 C g = input capacitance C g = input capacitance R eq = on resistance R eq = on resistance C int = intrinsic output capacitance ≈ C g C int = intrinsic output capacitance ≈ C g CgCg CLCL C int

Fall 06, Sep 19, 21ELEC / Lecture 617 Transistor Sizing for Performance Problem: If we increase W/L to make the charging or discharging of load capacitance faster, then the increased W increases the load for the driving gate Problem: If we increase W/L to make the charging or discharging of load capacitance faster, then the increased W increases the load for the driving gate C in =C g C L +SC g Increase W for faster charging of C L Faster charging Slower charging More power R eq /S

Fall 06, Sep 19, 21ELEC / Lecture 618 Delay of a CMOS Gate CMOS gate CLCL CgCg C int Propagation delay through the gate: t p = K 0.69 R eq (C int + C L ) ≈ K 0.69 R eq C g (1 + C L /C g ) = t p0 (1 + C L /C g ) where K depends upon V DD, V th, etc. Gate capacitance Intrinsic capacitance

Fall 06, Sep 19, 21ELEC / Lecture 619 R eq, C g, C int, and Width Sizing R eq : equivalent resistance of “on” transistor, proportional to L/W; scales as 1/S, S = width sizing factor R eq : equivalent resistance of “on” transistor, proportional to L/W; scales as 1/S, S = width sizing factor C g : gate capacitance, proportional to C ox WL; scales as S C g : gate capacitance, proportional to C ox WL; scales as S C int : intrinsic output capacitance ≈ C g, for submicron processes C int : intrinsic output capacitance ≈ C g, for submicron processes t p0 : intrinsic delay = K 0.69R eq C g, independent of sizing t p0 : intrinsic delay = K 0.69R eq C g, independent of sizing

Fall 06, Sep 19, 21ELEC / Lecture 620 Effective Fan-out, F Effective fan-out is defined as the ratio between the external load capacitance and the input capacitance: Effective fan-out is defined as the ratio between the external load capacitance and the input capacitance: F=C L /C g t p =t p0 (1 + F )

Fall 06, Sep 19, 21ELEC / Lecture 621 Sizing Through an Inverter Chain Cg1Cg1 Cg2Cg2 CLCL 12N C g2 = f2 C g1 t p1 = t p0 (1 + C g2 /C g1 ) t p2 = t p0 (1 + C g3 /C g2 )N t p =Σ t pj =t p0 Σ (1 + C gj+1 /C gj ) j=1j=1

Fall 06, Sep 19, 21ELEC / Lecture 622 Minimum Delay Sizing Equate partial derivatives of t p with respect to C gj to 0, for all j 1/C g1 – C g3 /C g2 2 = 0, etc. or C g2 2 = C g1 × C g3, etc. orC g2 /C g1 = C g3 /C g2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage: C L /C g1 = F = f N, t p = Nt p0 (1 + F 1/N )

Fall 06, Sep 19, 21ELEC / Lecture 623 Minimum Delay Sizing Equate partial derivatives of t p with respect to N to 0: dNt p0 (1 + F 1/N ) ───────── = 0 dN i.e., F 1/N – F 1/N (ln F)/N = 0, or ln (f N ) = N or ln f = 1 → f = e = 2.7 and N = ln F

Fall 06, Sep 19, 21ELEC / Lecture 624 Further Reading B. S. Cherkauer and E. G. Friedman, “A Unified Design Methodology for CMOS Tapered Buffers,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp , March 1995.

Fall 06, Sep 19, 21ELEC / Lecture 625 Sizing for Energy Minimization Main idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing. Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003.

Fall 06, Sep 19, 21ELEC / Lecture 626 Sizing for Energy Minimization Cg1Cg1 CLCL t p = t p0 [(1+ f ) + (1+ F/f )] = t p0 (2 + f + F/f ) F= C L /C g1, effective fan-out t p0 ~V DD /(V DD – V th ) for short channel Energy dissipation, E = V DD 2 C g1 (2 + 2f + F ) f 1 Minimum sized gate Cg1Cg1 fC g1 R eq /f R eq

Fall 06, Sep 19, 21ELEC / Lecture 627 Holding Delay Constant Reference circuit: f = 1, supply voltage = V ref Reference circuit: f = 1, supply voltage = V ref Size the circuit such that the delay of the new circuit is smaller than or equal to the reference circuit: Size the circuit such that the delay of the new circuit is smaller than or equal to the reference circuit: t p t p0 (2+f+F/f ) V DD V ref - V th 2+f+F/f t p t p0 (2+f+F/f ) V DD V ref - V th 2+f+F/f ── = ──────── = ── ──── ───── = 1 t pref t p0ref (3 +F ) V ref V DD - V th 3+F

Fall 06, Sep 19, 21ELEC / Lecture 628 Supply Voltage Vs. Sizing f V DD (volts) F= f opt ≈ √F V ref = 2.5V V th = 0.5V

Fall 06, Sep 19, 21ELEC / Lecture 629 Energy E V DD f + F ── = ─── ────── E ref V ref F

Fall 06, Sep 19, 21ELEC / Lecture 630 Normalized Energy Vs. Sizing f Normalized Energy F= f opt ≈ √F V ref = 2.5V V th = 0.5V

Fall 06, Sep 19, 21ELEC / Lecture 631 Summary Device sizing combined with supply voltage reduction reduces energy consumption. Device sizing combined with supply voltage reduction reduces energy consumption. For large fan-out energy reduction by a factor of 10 is possible. For large fan-out energy reduction by a factor of 10 is possible. An exception is F = 1 case, where the minimum size device is also the most effective one. An exception is F = 1 case, where the minimum size device is also the most effective one. Oversizing the devices increases energy consumption. Oversizing the devices increases energy consumption.