EECE476 Lecture 6: Designing a Single-Cycle CPU Datapath Chapter 5, Sections 5.2, 5.3 The University of British ColumbiaEECE 476© 2005 Guy Lemieux

2 Overview Brief look –Digital logic How to Design a CPU Datapath –MIPS Example

3 Digital Logic DQ D-type Flip-flop Clock (edge- triggered) S (Select input) A B F 0 1 Multiplexer D-type Flip-flop with Enable Clock (edge- triggered) DQ EN 0 1 DQ D Q (enable) Clock (edge- triggered)

4 Digital Logic 1 Bit DQ Clock (edge- triggered) EN 4 Bits Clock (edge- triggered) D3Q3 EN D2Q2 D1Q1 D0Q0 Registers N Bits DQ Clock (edge- triggered) EN

5 Digital Logic out in drive Tri-state Driver (Buffer) InDriveOut 00Z 10Z What is Z ??

6 Digital Logic Adder/Subtractor or ALU A B F Carry-out Add/sub or ALUop Carry-in

7 A Computer: ‘add r1,r0’ Behaviour: R1 ← R1 + R0 Operations: T ← R1 S ← R0 R1 ← T + S T,S are temp registers Register Transfer Language (RTL) DQ EN DQ DQ DQ R0 R1 T S driveR0 driveR1 driveALU loadR0 loadR1 loadT loadS

8 A Computer ‘add r2,r1,r0’ Behaviour: R2 ← R1 + R0 Operations: T ← R1 S ← R0 R2 ← T + S T,S are temp registers Register Transfer Language (RTL) DQ EN DQ DQ DQ R0 R1 T S driveR0 driveR1 driveALU loadR0 loadR1 loadT loadS DQ EN R2 driveR2 loadR2

9 Overview Brief look –Digital logic How to Design a CPU Datapath –MIPS Example

10 Designing a CPU: 5 Steps 1.Analyse the instruction set  datapath requirements –MIPS: ADD, SUB, ORI, LW, SW, BR –Meaning of each instruction given by RTL (register transfers) –2 types of registers: CPU/ISA registers, temporary registers 2.Datapath requirements  select the datapath components –ALU, register file, adder, data memory, etc 3.Assemble the datapath –Datapath must support planned register transfers –Ensure all instructions are supported 4.Analyse datapath control required for each instruction 5.Assemble the control logic Today, we’ll examine only Steps 1..3 Like good software development, there is overlap and iteration between the steps (successive refinement)!

11 Step 1a: Analyse ISA All MIPS instructions are 32 bits long. Three instruction formats: –R-type –I-type –J-type R: registers, I: immediate, J: jumps These formats intentionally chosen to simplify design optarget address bits26 bits oprsrtrdshamtfunct bits 5 bits oprsrt immediate bits16 bits5 bits

12 Step 1b: Analyse ISA Meaning of the fields: –op: operation of the instruction –rs, rt, rd: the source and destination register specifiers Destination is either rd (R-type), or rt (I-type) –shamt: shift amount –funct: selects the variant of the operation in the “op” field –immediate: address offset or immediate value –target address: target address of the jump instruction optarget address bits26 bits oprsrtrdshamtfunct bits 5 bits oprsrt immediate bits16 bits5 bits R-type I-type J-type

13 MIPS ISA: subset for today ADD and SUB –addU rd, rs, rt –subU rd, rs, rt OR Immediate: –ori rt, rs, imm16 LOAD and STORE Word –lw rt, rs, imm16 –sw rt, rs, imm16 BRANCH: –beq rs, rt, imm16 oprsrtrdshamtfunct bits 5 bits oprsrtimmediate bits16 bits5 bits oprsrtimmediate bits16 bits5 bits oprsrtimmediate bits16 bits5 bits

14 Step 2: Datapath Requirements REGISTER FILE MIPS ISA requires 32 registers, 32b each –Called a register file –Contains 32 entries –Each entry is 32b AddU rd,rs,rt or SubU rd,rs,rt –Read two sources rs, rt –Operation rs + rt or rs – rt –Write destination rd ← rs+/-rt Requirements –Read two registers (rs, rt) –Perform ALU operation –Write a third register (rd) RdReg1 RdReg2 WrReg WrData RdData1 RdData2 RegWrite REGFILE Register Numbers (5 bits ea) How to implement? ALU ALUop Result Zero?

15 Step 3: Datapath Assembly ADDU rd, rs, rtSUBU rd, rs, rt –Need an ALU Hook it up to REGISTER FILE REGFILE has 2 read ports (rs,rt), 1 write port (rd) RdReg1 RdReg2 WrReg WrData RdData1 RdData2 RegWrite REGFILE rs ALU ALUop Result Zero? Parameters Come From Instruction Fields rt rd Control Signals Depend Upon Instruction Fields Eg: ALUop = f(Instruction) = f(op, funct)

16 Steps 2 and 3: Datapath Components & Assembly, ORI Instruction ORI rt, rs, Imm16 –Need new ALUop for ‘OR’ function, hook up to REGFILE –1 read port (rs), 1 write port (rt), 1 const value (Imm16) RdReg1 RdReg2 WrReg WrData RdData1 RdData2 RegWrite REGFILE rs From Instruction rt rt rd ZERO- EXTEND ALU ALUop Result Zero? 16-bits Imm16 ALUsrc 0 1 X Control Signals Depend Upon Instruction Fields Eg: ALUsrc = f(Instruction) = f(op, funct)

17 Steps 2 and 3: Datapath Components & Assembly Must select proper destination, rd or rt –Depends on Instruction Type R-type may write rd I-type may write rt RdReg1 RdReg2 WrReg WrData RdData1 RdData2 REGFILE rs From Instruction rt rd ZERO- EXTEND ALU ALUop Result Zero? ALUsrc 0 1 RegDst bits Imm16 RegWrite

18 Steps 2 and 3: Datapath Components & Assembly LW rt, rs, Imm16 –Need Data Memory:data ← Mem[Addr] Addr is rs+Imm16, Imm16 is signed, use ALU for + –Store in rt:rt ← Mem[rs+Imm16] RdReg1 RdReg2 WrReg WrData RdData1 RdData2 REGFILE rs rt rd SIGN/ ZERO- EXTEND ALU ALUop Result Zero? ALUsrc 0 1 RegDst 1 0 Imm16 RegWrite Addr RdData MemtoReg 0 1 DATAMEM ExtOp

19 Steps 2 and 3: Datapath Components & Assembly SW rt, rs, Imm16 –Need Data Memory:Mem[Addr] ← data Addr is rs+Imm16, Imm16 is signed, use ALU for + –Store in Mem:Mem[rs+Imm16] ← rt RdReg1 RdReg2 WrReg WrData RdData1 RdData2 REGFILE rs rt rd SIGN/ ZERO- EXTEND ALU ALUop Result Zero? ALUsrc 0 1 RegDst 1 0 Imm16 RegWrite Addr RdData WrData MemtoReg 1 0 DATAMEM ExtOp MemWrite

20 Writes: Be Careful! Control Signal Timing Problem: write to data memory –Data can come anytime –Addr must come first –MemWrite must come after Addr Else? writes to wrong Addr! Solution: use ideal data memory –Assume everything works ok –How to fix this for real? –One solution: synchronous memory –Another solution: delay MemWr to come late Problems?: write to register file –Does RegWrite signal come after WrReg number? –When does the write to a register happen? –Read from same register as being written?